From: Capstone E. <cap...@gm...> - 2015-02-04 04:20:19
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On Wed, Feb 4, 2015 at 12:26 AM, Capstone Engine <cap...@gm...> wrote: > > > On Tue, Feb 3, 2015 at 5:44 AM, Edwin Cheng <edw...@gm...> wrote: > >> Hi all, >> >> I am working on the "Provide explicit registers" feature described in >> capstone github wiki page. >> The idea is based on using "ins" and "outs" description in MCInstrDesc >> X86Insts, (X86GenInstrInfo.inc) >> which is generated by llvm-tblgen. However, the X86Insts part was cut in >> capstone. >> I tried to generate myself but i found that the instruction set is not >> same as the trunk of llvm. So, >> >> 1. What is the version of LLVM for table generation (at least X86) ? >> > > thanks for contacting us! we already have something underway, but it would > be great to have you helped to speed up the process. > will send you more info later. > > i just pushed the work-in-progress to the "next" branch on Github. https://github.com/aquynh/capstone/tree/next you can find the mapping table in an array variable named "insn_ops" in arch/X86/X86Mapping.c currently this is not ready yet, so i commented it out. status: this table was auto-gen, so information can be incorrect, or missing. so it is a good idea to go thru & verify every instructions. please send pull request on Github if you can update this table. thanks, Q |