From: GROETZ, M. A C. U. A. AFRL/R. <mic...@us...> - 2015-01-22 13:43:57
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>a quick question: do you have any problem with the TestX86.java code? what >is the output of it? ------------------------ Here's the output from TexstX86.java. I only included 32 and 64 bit (I'm running on a 64 bit machine). If you need all of the output let me know. Thanks You for your help. -Mike ------------------------------------ Platform: X86 32 (Intel syntax) Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 Disasm: 0x1000: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x4c disp: 0x8 sib: 0x32 sib_base: edx sib_index: esi sib_scale: 1 op_count: 2 operands[0].type: REG = ecx operands[0].size: 4 operands[1].type: MEM operands[1].mem.base: REG = edx operands[1].mem.index: REG = esi operands[1].mem.disp: 0x8 operands[1].size: 4 0x1004: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x01 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0xd8 disp: 0x0 sib: 0x0 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[1].type: REG = ebx operands[1].size: 4 0x1006: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x81 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0xc6 disp: 0x0 sib: 0x0 imm_count: 1 imms[1]: 0x1234 op_count: 2 operands[0].type: REG = esi operands[0].size: 4 operands[1].type: IMM = 0x1234 operands[1].size: 4 0x100c: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x05 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x0 disp: 0x0 sib: 0x0 imm_count: 1 imms[1]: 0x123 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[1].type: IMM = 0x123 operands[1].size: 4 0x1011: null null Prefix: 0x00 0x36 0x00 0x00 Opcode: 0x8b 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x84 disp: 0x123 sib: 0x91 sib_base: ecx sib_index: edx sib_scale: 4 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[1].type: MEM operands[1].mem.segment: REG = ss operands[1].mem.base: REG = ecx operands[1].mem.index: REG = edx operands[1].mem.scale: 4 operands[1].mem.disp: 0x123 operands[1].size: 4 0x1019: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x41 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x0 disp: 0x0 sib: 0x0 op_count: 1 operands[0].type: REG = ecx operands[0].size: 4 0x101a: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x84 disp: 0x6789 sib: 0x39 sib_base: ecx sib_index: edi sib_scale: 1 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[1].type: MEM operands[1].mem.base: REG = ecx operands[1].mem.index: REG = edi operands[1].mem.disp: 0x6789 operands[1].size: 4 0x1021: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x87 disp: 0x6789 sib: 0x0 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[1].type: MEM operands[1].mem.base: REG = edi operands[1].mem.disp: 0x6789 operands[1].size: 4 0x1027: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0xb4 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x0 disp: 0x0 sib: 0x0 imm_count: 1 imms[1]: 0xffffffffffffffc6 op_count: 2 operands[0].type: REG = ah operands[0].size: 1 operands[1].type: IMM = 0xffffffffffffffc6 operands[1].size: 1 0x1029: ------------------------------------------------------------------ Platform: X86 64 (Intel syntax) Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 Disasm: 0x1000: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x55 0x00 0x00 0x00 rex: 0x0 addr_size: 8 modrm: 0x0 disp: 0x0 sib: 0x0 op_count: 1 operands[0].type: REG = rbp operands[0].size: 8 0x1001: null null Prefix: 0x00 0x00 0x00 0x00 Opcode: 0x8b 0x00 0x00 0x00 rex: 0x48 addr_size: 8 modrm: 0x5 disp: 0x13b8 sib: 0x0 op_count: 2 operands[0].type: REG = rax operands[0].size: 8 operands[1].type: MEM operands[1].mem.base: REG = rip operands[1].mem.disp: 0x13b8 operands[1].size: 8 0x1008: |