Re: [Capstone-users] Wrong detailed instruction info for ARM BL

[Capstone E. <cap...@gm...>]

On Thu, Dec 25, 2014 at 6:31 AM, Der Rek <der...@ya...> wrote:

> Hi,
>
> this is the first time I'm using a mailing list, please forgive me when
> I'm doing something wrong.
>
> I noticed when disassembling an ARM mode "BL <label>" instr, the detailed
> instr info in cs_insn->detail
> is wrong.
> cs_insn->detail->regs_read_count is 0x01 and regs_read[0] is 0x0c, which
> is ARM_REG_SP in enum arm_reg defined in arm.h.
> However, the expected result should be like this I guess:
> cs_insn->detail->regs_read_count should be 0x01   and regs_read[0] should
> be ARM_REG_PC (which is 0x0B in the arm_reg enum).
> "BL" is branch with link. Which means SP (= stack pointer) isn't involved
> at all.
> In addition, regs_write_count is 0x01, but it should be 0x02. ARM_REG_PC
> is missing in regs_write (ofc the program counter gets updated on jumps).
>

on the missing of REG_PC, keep in mind that regs_write[] just contains
registers *implicitly* modified by instructions, and PC register is never
considered.

thanks.