Menu
▾
▴
[Can-svn] SF.net SVN: can: [837] trunk/firmware/arm/str
|
From: <ak...@us...> - 2008-02-11 17:33:31
|
Revision: 837
http://can.svn.sourceforge.net/can/?rev=837&view=rev
Author: akhe
Date: 2008-02-11 09:33:26 -0800 (Mon, 11 Feb 2008)
Log Message:
-----------
Added starter code for VSCP demo node for str73x
Modified Paths:
--------------
trunk/firmware/arm/str/cantest_str73x_gcc/main.c
trunk/firmware/arm/str/cantest_str73x_gcc/vectors.c
trunk/firmware/arm/str/common/sysTime.c
Added Paths:
-----------
trunk/firmware/arm/str/vscp_node_str73x_gcc/
trunk/firmware/arm/str/vscp_node_str73x_gcc/Makefile
trunk/firmware/arm/str/vscp_node_str73x_gcc/Readme.txt
trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-RAM.ld
trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-ROM.ld
trunk/firmware/arm/str/vscp_node_str73x_gcc/main.c
trunk/firmware/arm/str/vscp_node_str73x_gcc/startup.s
trunk/firmware/arm/str/vscp_node_str73x_gcc/vector.s
trunk/firmware/arm/str/vscp_node_str73x_gcc/vectors.c
trunk/firmware/arm/str/vscp_node_str73x_gcc/vectors.h
trunk/firmware/arm/str/vscp_node_str73x_gcc/vscpnode.pnproj
trunk/firmware/arm/str/vscp_node_str73x_gcc/vscpnode.pnps
Modified: trunk/firmware/arm/str/cantest_str73x_gcc/main.c
===================================================================
--- trunk/firmware/arm/str/cantest_str73x_gcc/main.c 2008-02-11 17:19:34 UTC (rev 836)
+++ trunk/firmware/arm/str/cantest_str73x_gcc/main.c 2008-02-11 17:33:26 UTC (rev 837)
@@ -289,12 +289,9 @@
// wait until end of transmission
CAN_WaitEndOfTx( CAN0 );
- GPIO_BitWrite( GPIO0, LD16, Bit_SET ); // LED16;
-
// release the TX message object
CAN_ReleaseTxMessage( CAN0, CAN0_TX_MSGOBJ );
-
// Check for a data frame
if ( CAN_ReceiveMessage( CAN0, CAN0_RX_MSGOBJ, FALSE, &RxCan0Msg ) ) {
@@ -327,10 +324,7 @@
} // Received frame
-
- delay_ms( 500 );
-
-/*
+
// Start ADC conversion
ADC_ConversionCmd( ADC_ConversionStart );
buffer[8] = get1Digit( Conversion_Value );
@@ -349,9 +343,11 @@
}
GPIO_WordWrite( GPIO0, CPIO_Value );
-*/
- }
+ // Wait for 500 ms
+ delay_ms( 500 );
+
+ } // while
}
Modified: trunk/firmware/arm/str/cantest_str73x_gcc/vectors.c
===================================================================
--- trunk/firmware/arm/str/cantest_str73x_gcc/vectors.c 2008-02-11 17:19:34 UTC (rev 836)
+++ trunk/firmware/arm/str/cantest_str73x_gcc/vectors.c 2008-02-11 17:33:26 UTC (rev 837)
@@ -765,10 +765,13 @@
*******************************************************************************/
void ADC_IRQHandler (void)
{
- Conversion_Value = ADC_GetConversionValue(ADC_CHANNEL0);
- /* Clear EOC Interrupt pending bit */
+ // Get ADC value
+ Conversion_Value = ADC_GetConversionValue( ADC_CHANNEL0 );
+
+ // Clear EOC Interrupt pending bit
ADC_FlagClear( ADC_FLAG_EOC );
- /* Clear the last Analog Watchdog0 comparison result */
+
+ // Clear the last Analog Watchdog0 comparison result */
ADC_FlagClear( ADC_FLAG_AnalogWatchdog0_HighThresold | ADC_FLAG_AnalogWatchdog0_LowThresold );
ADC_ConversionCmd (ADC_ConversionStop);
Modified: trunk/firmware/arm/str/common/sysTime.c
===================================================================
--- trunk/firmware/arm/str/common/sysTime.c 2008-02-11 17:19:34 UTC (rev 836)
+++ trunk/firmware/arm/str/common/sysTime.c 2008-02-11 17:33:26 UTC (rev 837)
@@ -54,9 +54,10 @@
TB_Init( TB2, &TB_InitStructure );
TB_ITConfig( TB2, ENABLE );
- TB_Cmd( TB2, ENABLE ); // Start the timer
EIC_IRQChannelConfig( TB2_IRQChannel, ENABLE ); // Enable IRQ
+
+ TB_Cmd( TB2, ENABLE ); // Enable the timer
}
/******************************************************************************
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/Makefile
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/Makefile (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/Makefile 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,497 @@
+# Hey Emacs, this is a -*- makefile -*-
+#
+# WinARM template makefile
+# by Giacomo Fazio and Antonio Nasca, Catania, Italy
+# <gia...@gm...>
+# <ant...@ho...>
+#
+# based on the WinARM template makefile written by Martin Thomas
+# Released to the Public Domain
+# Please read the make user manual!
+#
+#
+# On command line:
+#
+# make all = Make software.
+#
+# make clean = Clean out built project files.
+#
+# make program = Download the hex file to the device
+#
+# (TODO: make filename.s = Just compile filename.c into the assembler code only)
+#
+# To rebuild project do "make clean" then "make all".
+# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe)
+TCHAIN = arm-elf
+#TCHAIN = arm-none-eabi
+
+#USE_THUMB_MODE = YES
+USE_THUMB_MODE = NO
+
+# MCU name and submodel
+MCU = arm7tdmi
+SUBMDL = STR73x
+
+## Create ROM-Image
+RUN_MODE=ROM_RUN
+## Create RAM-Image
+#RUN_MODE=RAM_RUN
+
+## not supported in this example:
+## Exception-Vector placement only supported for "ROM_RUN"
+## (placement settings ignored when using "RAM_RUN")
+## - Exception vectors in ROM:
+#VECTOR_LOCATION=VECTORS_IN_ROM
+## - Exception vectors in RAM:
+#VECTOR_LOCATION=VECTORS_IN_RAM
+
+
+# Target file name (without extension).
+TARGET = main
+
+# List C source files here. (C dependencies are automatically generated.)
+# use file-extension c for "c-only"-files
+SRC = $(TARGET).c ../common/73x_lcd.c ../common/sysTime.c ../common/delay.c
+
+# List C source files here which must be compiled in ARM-Mode.
+# use file-extension c for "c-only"-files
+SRCARM = vectors.c
+# thumb is possible too for vectors.c - keep ARM, TODO: profile
+
+# List C++ source files here.
+# use file-extension cpp for C++-files (use extension .cpp)
+CPPSRC =
+
+# List C++ source files here which must be compiled in ARM-Mode.
+# use file-extension cpp for C++-files (use extension .cpp)
+#CPPSRCARM = $(TARGET).cpp
+CPPSRCARM =
+
+# List Assembler source files here.
+# Make them always end in a capital .S. Files ending in a lowercase .s
+# will not be considered source files but generated files (assembler
+# output from the compiler), and will be deleted upon "make clean"!
+# Even though the DOS/Win* filesystem matches both .s and .S the same,
+# it will preserve the spelling of the filenames, and gcc itself does
+# care about how the name is spelled on its command-line.
+ASRC =
+
+# List Assembler source files here which must be assembled in ARM-Mode..
+ASRCARM = vector.S startup.S
+
+# Path to Linker-Scripts
+LINKERSCRIPTPATH = .
+
+## Output format. (can be ihex or binary or both)
+## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision)
+#FORMAT = ihex
+#FORMAT = binary
+FORMAT = both
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+#OPT = s
+OPT = 0
+
+## Using the Atmel AT91_lib produces warning with
+## the default warning-levels.
+## yes - disable these warnings; no - keep default settings
+#AT91LIBNOWARN = yes
+AT91LIBNOWARN = no
+
+# Debugging format.
+# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2.
+# AVR (extended) COFF requires stabs, plus an avr-objcopy run.
+#DEBUG = stabs
+DEBUG = dwarf-2
+
+# List any extra directories to look for include files here.
+# Each directory must be seperated by a space.
+EXTRAINCDIRS = "K:/include" ../common/str73x_lib/include
+
+# List any extra directories to look for library files here.
+# Each directory must be seperated by a space.
+#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4
+EXTRA_LIBDIRS = K:/lib ../common/str73x_lib
+
+
+# Compiler flag to set the C Standard level.
+# c89 - "ANSI" C
+# gnu89 - c89 plus GCC extensions
+# c99 - ISO C99 standard (not yet fully implemented)
+# gnu99 - c99 plus GCC extensions
+CSTANDARD = -std=gnu99
+
+# Place -D or -U options for C here
+CDEFS = -D$(RUN_MODE)
+
+# Place -I options here
+CINCS =
+
+# Place -D or -U options for ASM here
+ADEFS = -D$(RUN_MODE)
+
+ifdef VECTOR_LOCATION
+CDEFS += -D$(VECTOR_LOCATION)
+ADEFS += -D$(VECTOR_LOCATION)
+endif
+
+CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+
+# Compiler flags.
+
+ifeq ($(USE_THUMB_MODE),YES)
+THUMB = -mthumb
+THUMB_IW = -mthumb-interwork
+else
+THUMB =
+THUMB_IW =
+endif
+
+# -g*: generate debugging information
+# -O*: optimization level
+# -f...: tuning, see GCC manual and avr-libc documentation
+# -Wall...: warning level
+# -Wa,...: tell GCC to pass this to the assembler.
+# -adhlns...: create assembler listing
+#
+# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
+CFLAGS = -g$(DEBUG)
+CFLAGS += $(CDEFS) $(CINCS)
+CFLAGS += -O$(OPT)
+CFLAGS += -Wall -Wcast-align -Wimplicit
+CFLAGS += -Wpointer-arith -Wswitch
+CFLAGS += -ffunction-sections -fdata-sections
+CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused
+CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<)
+CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+
+# flags only for C
+CONLYFLAGS += -Wnested-externs
+CONLYFLAGS += $(CSTANDARD)
+
+ifneq ($(AT91LIBNOWARN),yes)
+#AT91-lib warnings with:
+CFLAGS += -Wcast-qual
+CONLYFLAGS += -Wmissing-prototypes
+CONLYFLAGS += -Wstrict-prototypes
+CONLYFLAGS += -Wmissing-declarations
+endif
+
+# flags only for C++ (arm-elf-g++)
+# CPPFLAGS = -fno-rtti -fno-exceptions
+CPPFLAGS =
+
+# Assembler flags.
+# -Wa,...: tell GCC to pass this to the assembler.
+# -ahlns: create listing
+# -g$(DEBUG): have the assembler create line number information
+ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG)
+
+
+#Additional libraries.
+
+# Extra libraries
+# Each library-name must be seperated by a space.
+# To add libxyz.a, libabc.a and libefsl.a:
+# EXTRA_LIBS = xyz abc efsl
+#EXTRA_LIBS = efsl
+EXTRA_LIBS = STR73x_lib
+
+#Support for newlibc-lpc (file: libnewlibc-lpc.a)
+#NEWLIBLPC = -lnewlib-lpc
+
+MATH_LIB = -lm
+
+# CPLUSPLUS_LIB = -lstdc++
+
+
+# Linker flags.
+# -Wl,...: tell GCC to pass this to linker.
+# -Map: create map file
+# --cref: add cross reference to map file
+LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections
+LDFLAGS += -lc
+LDFLAGS += $(NEWLIBLPC) $(MATH_LIB)
+LDFLAGS += -lc -lgcc
+LDFLAGS += $(CPLUSPLUS_LIB)
+LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS))
+LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS))
+
+# Set Linker-Script Depending On Selected Memory and Controller
+ifeq ($(RUN_MODE),RAM_RUN)
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld
+else
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld
+endif
+
+
+# Define directories, if needed.
+## DIRARM = c:/WinARM/
+## DIRARMBIN = $(DIRAVR)/bin/
+## DIRAVRUTILS = $(DIRAVR)/utils/bin/
+
+# Define programs and commands.
+SHELL = sh
+CC = $(TCHAIN)-gcc
+CPP = $(TCHAIN)-g++
+AR = $(TCHAIN)-ar
+OBJCOPY = $(TCHAIN)-objcopy
+OBJDUMP = $(TCHAIN)-objdump
+SIZE = $(TCHAIN)-size
+NM = $(TCHAIN)-nm
+REMOVE = rm -f
+REMOVEDIR = rm -f -r
+COPY = cp
+
+# Define Messages
+# English
+MSG_ERRORS_NONE = Errors: none
+MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------"
+MSG_END = -------- end --------
+MSG_SIZE_BEFORE = Size before:
+MSG_SIZE_AFTER = Size after:
+MSG_FLASH = Creating load file for Flash:
+MSG_EXTENDED_LISTING = Creating Extended Listing:
+MSG_SYMBOL_TABLE = Creating Symbol Table:
+MSG_LINKING = Linking:
+MSG_COMPILING = Compiling C:
+MSG_COMPILING_ARM = "Compiling C (ARM-only):"
+MSG_COMPILINGCPP = Compiling C++:
+MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):"
+MSG_ASSEMBLING = Assembling:
+MSG_ASSEMBLING_ARM = "Assembling (ARM-only):"
+MSG_CLEANING = Cleaning project:
+MSG_FORMATERROR = Can not handle output-format
+MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now.
+
+# Define all object files.
+COBJ = $(SRC:.c=.o)
+AOBJ = $(ASRC:.S=.o)
+COBJARM = $(SRCARM:.c=.o)
+AOBJARM = $(ASRCARM:.S=.o)
+CPPOBJ = $(CPPSRC:.cpp=.o)
+CPPOBJARM = $(CPPSRCARM:.cpp=.o)
+
+# Define all listing files.
+LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst)
+LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst)
+
+# Compiler flags to generate dependency files.
+### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d
+GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d
+
+# Combine all necessary flags and optional flags.
+# Add target processor to flags.
+ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS)
+ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS)
+
+
+# Default target.
+all: begin gccversion sizebefore build sizeafter finished end
+
+ifeq ($(FORMAT),ihex)
+build: elf hex lss sym
+hex: $(TARGET).hex
+IMGEXT=hex
+else
+ifeq ($(FORMAT),binary)
+build: elf bin lss sym
+bin: $(TARGET).bin
+IMGEXT=bin
+else
+ifeq ($(FORMAT),both)
+build: elf hex bin lss sym
+hex: $(TARGET).hex
+bin: $(TARGET).bin
+else
+$(error "$(MSG_FORMATERROR) $(FORMAT)")
+endif
+endif
+endif
+
+elf: $(TARGET).elf
+lss: $(TARGET).lss
+sym: $(TARGET).sym
+
+# Eye candy.
+begin:
+ @echo
+ @echo $(MSG_BEGIN)
+
+finished:
+ @echo $(MSG_ERRORS_NONE)
+
+end:
+ @echo $(MSG_END)
+ @echo
+
+
+# Display size of file.
+HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
+ELFSIZE = $(SIZE) -A $(TARGET).elf
+sizebefore:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi
+
+sizeafter:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi
+
+
+# Display compiler version information.
+gccversion :
+ @$(CC) --version
+
+# FLASH Programming with OPENOCD
+
+# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe)
+# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded
+OPENOCD_DIR = 'C:\Program Files\openocd-r247\bin\'
+
+# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger)
+#OPENOCD = $(OPENOCD_DIR)openocd-pp.exe
+OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe
+
+# specify OpenOCD configuration file (pick the one for your device)
+#OPENOCD_CFG = C:\openocd-configs\str73x-configs\str73x_signalyzer-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str73x-configs\str73x_jtagkey-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str73x-configs\str73x_armusbocd-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str73x-configs\str73x_pp-flash-program.cfg
+#OPENOCD_CFG = "D:\development\armdev\str73x open source development\Code\Windows\openocd-configs\str73x-configs\str73x_jtagkey-flash-program.cfg"
+OPENOCD_CFG = "c:\str73x_jtagkey-flash-program.cfg"
+
+program:
+ @echo
+ @echo "Flash Programming with OpenOCD..."
+ $(OPENOCD) -f $(OPENOCD_CFG)
+ @echo
+ @echo
+ @echo "Flash Programming Finished."
+
+
+# Create final output file (.hex) from ELF output file.
+%.hex: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O ihex $< $@
+
+# Create final output file (.bin) from ELF output file.
+%.bin: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O binary $< $@
+
+
+# Create extended listing file from ELF output file.
+# testing: option -C
+%.lss: %.elf
+ @echo
+ @echo $(MSG_EXTENDED_LISTING) $@
+ $(OBJDUMP) -h -S -C $< > $@
+
+
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+ @echo
+ @echo $(MSG_SYMBOL_TABLE) $@
+ $(NM) -n $< > $@
+
+
+# Link: create ELF output file from object files.
+.SECONDARY : $(TARGET).elf
+.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+ @echo
+ @echo $(MSG_LINKING) $@
+ $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+
+# Compile: create object files from C source files. ARM/Thumb
+$(COBJ) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING) $<
+ $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C source files. ARM-only
+$(COBJARM) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING_ARM) $<
+ $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM/Thumb
+$(CPPOBJ) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP) $<
+ $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM-only
+$(CPPOBJARM) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP_ARM) $<
+ $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C source files. ARM/Thumb
+## does not work - TODO - hints welcome
+##$(COBJ) : %.s : %.c
+## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM/Thumb
+$(AOBJ) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING) $<
+ $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM-only
+$(AOBJARM) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING_ARM) $<
+ $(CC) -c $(ALL_ASFLAGS) $< -o $@
+
+
+# Target: clean project.
+clean: begin clean_list finished end
+
+
+clean_list :
+ @echo
+ @echo $(MSG_CLEANING)
+ $(REMOVE) $(TARGET).hex
+ $(REMOVE) $(TARGET).bin
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).elf
+ $(REMOVE) $(TARGET).map
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).a90
+ $(REMOVE) $(TARGET).sym
+ $(REMOVE) $(TARGET).lnk
+ $(REMOVE) $(TARGET).lss
+ $(REMOVE) $(COBJ)
+ $(REMOVE) $(CPPOBJ)
+ $(REMOVE) $(AOBJ)
+ $(REMOVE) $(COBJARM)
+ $(REMOVE) $(CPPOBJARM)
+ $(REMOVE) $(AOBJARM)
+ $(REMOVE) $(LST)
+ $(REMOVE) $(SRC:.c=.s)
+ $(REMOVE) $(SRC:.c=.d)
+ $(REMOVE) $(SRCARM:.c=.s)
+ $(REMOVE) $(SRCARM:.c=.d)
+ $(REMOVE) $(CPPSRC:.cpp=.s)
+ $(REMOVE) $(CPPSRC:.cpp=.d)
+ $(REMOVE) $(CPPSRCARM:.cpp=.s)
+ $(REMOVE) $(CPPSRCARM:.cpp=.d)
+ $(REMOVEDIR) .dep | exit 0
+
+
+# Include the dependency files.
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+
+# Listing of phony targets.
+.PHONY : all begin finish end sizebefore sizeafter gccversion \
+build elf hex bin lss sym clean clean_list program
+
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/Readme.txt
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/Readme.txt (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/Readme.txt 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,14 @@
+Simple CAN test sample
+====================
+
+Ake Hedman, D of Scandinavia ak...@do..., http://www.dofscandinavia.com
+
+This file is built for the IAR str73x test board.
+
+The sample code send a CAN frame every 500 ms and display a "RECEIVE CAN MESSAGE"
+on the second line of the LCD if a CAN message with id 0x123, length=4 and
+data=1,2,4,8 is received. If another msg is received the line is cleared.
+
+CAN bitrate is 500 kbps.
+
+Based on a sample from ST
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-RAM.ld
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-RAM.ld (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-RAM.ld 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,228 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/* Stack Sizes */
+
+ _STACKSIZE = 1024;
+ _STACKSIZE_IRQ = 256;
+ _STACKSIZE_FIQ = 256;
+ _STACKSIZE_SVC = 0;
+ _STACKSIZE_ABT = 0;
+ _STACKSIZE_UND = 0;
+ _HEAPSIZE = 1024;
+
+/* Memory Definitions */
+
+MEMORY
+{
+ DATA (rw) : ORIGIN = 0xA0000000, LENGTH = 0x00004000
+}
+
+/* Section Definitions */
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+
+ .text :
+ {
+ KEEP(*(.vectrom))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t .glue_7)
+ KEEP(*(.fini))
+ *(.gcc_except_table)
+ } >DATA =0
+ . = ALIGN(4);
+
+ /* .ctors .dtors are used for c++ constructors/destructors */
+
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ } >DATA
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ } >DATA
+
+ /* .rodata section which is used for read-only data (constants) */
+
+ .rodata :
+ {
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >DATA
+ . = ALIGN(4);
+
+ _vectext = .;
+ PROVIDE (vectext = .);
+
+ .vect : AT (_vectext)
+ {
+ _vecstart = .;
+ KEEP(*(.vectram))
+ _vecend = .;
+ } >DATA
+
+ _etext = _vectext + SIZEOF(.vect);
+ PROVIDE (etext = .);
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_etext)
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ } >DATA
+ . = ALIGN(4);
+
+ __data_start = .;
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* .bss section which is used for uninitialized data */
+
+ .bss :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >DATA
+ . = ALIGN(4);
+ __bss_end__ = .;
+
+ _end = .;
+ PROVIDE(end = .);
+
+ /* .heap section which is used for memory allocation */
+
+ .heap (NOLOAD) :
+ {
+ __heap_start__ = .;
+ *(.heap)
+ . = MAX(__heap_start__ + _HEAPSIZE , .);
+ } >DATA
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ /* .stack section - user mode stack */
+
+ .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_start__ = .;
+ *(.stack)
+ . = MAX(__stack_start__ + _STACKSIZE , .);
+ } >DATA
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ /* .stack_irq section */
+
+ .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq)
+ . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .);
+ } >DATA
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ /* .stack_fiq section */
+
+ .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq)
+ . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .);
+ } >DATA
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ /* .stack_svc section */
+
+ .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc)
+ . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .);
+ } >DATA
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ /* .stack_abt section */
+
+ .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt)
+ . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .);
+ } >DATA
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ /* .stack_und section */
+
+ .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_und_start__ = .;
+ *(.stack_und)
+ . = MAX(__stack_und_start__ + _STACKSIZE_UND , .);
+ } >DATA
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-ROM.ld
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-ROM.ld (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/STR73x-ROM.ld 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,231 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/* Stack Sizes */
+
+ _STACKSIZE = 1024;
+ _STACKSIZE_IRQ = 256;
+ _STACKSIZE_FIQ = 256;
+ _STACKSIZE_SVC = 0;
+ _STACKSIZE_ABT = 0;
+ _STACKSIZE_UND = 0;
+ _HEAPSIZE = 1024;
+
+/* Memory Definitions */
+
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ DATA (rw) : ORIGIN = 0xA0000000, LENGTH = 0x00004000
+}
+
+/* Section Definitions */
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+
+ .text :
+ {
+ KEEP(*(.vectrom))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t .glue_7)
+ KEEP(*(.fini))
+ *(.gcc_except_table)
+ } >CODE =0
+ . = ALIGN(4);
+
+ /* .ctors .dtors are used for c++ constructors/destructors */
+
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ } >CODE
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ } >CODE
+
+ /* .rodata section which is used for read-only data (constants) */
+
+ .rodata :
+ {
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >CODE
+ . = ALIGN(4);
+
+ _vectext = .;
+ PROVIDE (vectext = .);
+
+ .vect : AT (_vectext)
+ {
+ _vecstart = .;
+ KEEP(*(.vectram))
+ _vecend = .;
+ } >DATA
+
+ _etext = _vectext + SIZEOF(.vect);
+ PROVIDE (etext = .);
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_etext)
+ {
+ __data_start = .;
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ . = ALIGN(4);
+ *(.fastrun .fastrun.*)
+ } >DATA
+ . = ALIGN(4);
+
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* .bss section which is used for uninitialized data */
+
+ .bss :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >DATA
+ . = ALIGN(4);
+ __bss_end__ = .;
+
+ _end = .;
+ PROVIDE(end = .);
+
+ /* .heap section which is used for memory allocation */
+
+ .heap (NOLOAD) :
+ {
+ __heap_start__ = .;
+ *(.heap)
+ . = MAX(__heap_start__ + _HEAPSIZE , .);
+ } >DATA
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ /* .stack section - user mode stack */
+
+ .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_start__ = .;
+ *(.stack)
+ . = MAX(__stack_start__ + _STACKSIZE , .);
+ } >DATA
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ /* .stack_irq section */
+
+ .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq)
+ . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .);
+ } >DATA
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ /* .stack_fiq section */
+
+ .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq)
+ . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .);
+ } >DATA
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ /* .stack_svc section */
+
+ .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc)
+ . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .);
+ } >DATA
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ /* .stack_abt section */
+
+ .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt)
+ . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .);
+ } >DATA
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ /* .stack_und section */
+
+ .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_und_start__ = .;
+ *(.stack_und)
+ . = MAX(__stack_und_start__ + _STACKSIZE_UND , .);
+ } >DATA
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/main.c
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/main.c (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/main.c 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,635 @@
+/******************** (C) COPYRIGHT 2005 STMicroelectronics **********************
+* File Name : main.c
+* Author : MCD Application Team
+* Date First Issued : 09/27/2005 : V1.0
+* Description : Main program body
+**********************************************************************************
+* History:
+* 09/27/2005 : V1.0
+**********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*********************************************************************************/
+
+/* Standard include ------------------------------------------------------------*/
+#include "73x_lib.h"
+#include "../common/73x_lcd.h"
+#include "../common/systime.h"
+#include "../common/delay.h"
+
+// Prototypes
+void wait( void );
+void MCLK_Config (void);
+void CAN0_Demo_Polling( void );
+void CAN0_Demo_Interrupt(void);
+unsigned int get1000Digit( unsigned int val );
+unsigned int get100Digit( unsigned int val );
+unsigned int get10Digit( unsigned int val );
+unsigned int get1Digit( unsigned int val );
+
+// Peripherals Init Structures
+GPIO_InitTypeDef GPIO0_InitStructure;
+GPIO_InitTypeDef GPIO3_InitStructure;
+ADC_InitTypeDef ADC_InitStructure;
+CMU_InitTypeDef CMU_InitStructure;
+RTC_InitTypeDef RTC_InitStructure;
+
+GPIO_InitTypeDef CAN0_RX;
+GPIO_InitTypeDef CAN0_TX;
+GPIO_InitTypeDef CAN1_RX;
+GPIO_InitTypeDef CAN1_TX;
+GPIO_InitTypeDef CAN2_RX;
+GPIO_InitTypeDef CAN2_TX;
+GPIO_InitTypeDef Led_Config;
+
+// define the LEDs
+#define LD1 GPIO_PIN_0
+#define LD2 GPIO_PIN_1
+#define LD3 GPIO_PIN_2
+#define LD4 GPIO_PIN_3
+#define LD5 GPIO_PIN_4
+#define LD6 GPIO_PIN_5
+#define LD7 GPIO_PIN_6
+#define LD8 GPIO_PIN_7
+#define LD9 GPIO_PIN_8
+#define LD10 GPIO_PIN_9
+#define LD11 GPIO_PIN_10
+#define LD12 GPIO_PIN_11
+#define LD13 GPIO_PIN_12
+#define LD14 GPIO_PIN_13
+#define LD15 GPIO_PIN_14
+#define LD16 GPIO_PIN_15
+
+// buffer for receive messages
+canmsg RxCan0Msg;
+
+// array of pre-defined transmit messages
+canmsg TxCan0Msg[ 2 ] = {
+ { CAN_STD_ID,
+ 0x123,
+ 4,
+ { 0x01, 0x02, 0x04, 0x08 } },
+ { CAN_EXT_ID,
+ 0x12345678,
+ 8,
+ { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 } }
+};
+
+// buffer for receive messages
+canmsg RxCan1Msg;
+
+// array of pre-defined transmit messages
+canmsg TxCan1Msg[2] = {
+ { CAN_STD_ID, 0x123, 4, { 0x01, 0x02, 0x04, 0x08 } },
+ { CAN_EXT_ID, 0x12345678, 8, { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 } }
+};
+
+// buffer for receive messages
+canmsg RxCan2Msg;
+
+// array of pre-defined transmit messages
+canmsg TxCan2Msg[2] = {
+ { CAN_STD_ID, 0x123, 4, { 0x01, 0x02, 0x04, 0x08 } },
+ { CAN_EXT_ID, 0x12345678, 8, { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 } }
+};
+
+// used message object numbers
+enum {
+ CAN0_TX_MSGOBJ = 0,
+ CAN0_RX_MSGOBJ = 1
+};
+enum {
+ CAN1_TX_MSGOBJ = 0,
+ CAN1_RX_MSGOBJ = 1
+};
+enum {
+ CAN2_TX_MSGOBJ = 0,
+ CAN2_RX_MSGOBJ = 1
+};
+
+u16 Conversion_Value = 0;
+u8 buffer[11] = "ADC: ";
+
+
+
+/* Private function prototypes -------------------------------------------------*/
+
+/* Interface functions ---------------------------------------------------------*/
+
+/* Private functions -----------------------------------------------------------*/
+
+
+int main(void)
+{
+ u32 CPIO_Value;
+
+#ifdef LIBDEBUG
+ libdebug();
+#endif
+
+ MCLK_Config();
+
+ // Enable clock on both CAN channels
+ CFG_PeripheralClockConfig( CFG_CLK_CAN0, ENABLE );
+ CFG_PeripheralClockConfig( CFG_CLK_CAN1, ENABLE );
+
+ CFG_PeripheralClockConfig( CFG_CLK_GPIO0, ENABLE );
+ CFG_PeripheralClockConfig( CFG_CLK_GPIO1, ENABLE );
+ CFG_PeripheralClockConfig( CFG_CLK_GPIO2, ENABLE );
+ CFG_PeripheralClockConfig( CFG_CLK_GPIO6, ENABLE );
+
+ Led_Config.GPIO_Mode = GPIO_Mode_OUT_PP;
+ Led_Config.GPIO_Pins = 0xFFFF;
+ GPIO_Init( GPIO0, &Led_Config );
+
+ GPIO3_InitStructure.GPIO_Mode = GPIO_Mode_HI_AIN_TRI;
+ GPIO3_InitStructure.GPIO_Pins = GPIO_PIN_ALL;
+ GPIO_Init( GPIO3, &GPIO3_InitStructure );
+
+ CAN0_RX.GPIO_Mode = GPIO_Mode_IN_TRI_TTL;
+ CAN0_RX.GPIO_Pins = GPIO_PIN_14;
+ GPIO_Init( GPIO1, &CAN0_RX );
+
+ CAN0_TX.GPIO_Mode = GPIO_Mode_AF_PP;
+ CAN0_TX.GPIO_Pins = GPIO_PIN_15;
+ GPIO_Init( GPIO1, &CAN0_TX );
+
+ CAN1_RX.GPIO_Mode = GPIO_Mode_IN_TRI_TTL;
+ CAN1_RX.GPIO_Pins = GPIO_PIN_1;
+ GPIO_Init( GPIO2, &CAN1_RX );
+
+ CAN1_TX.GPIO_Mode = GPIO_Mode_AF_PP;
+ CAN1_TX.GPIO_Pins = GPIO_PIN_2;
+ GPIO_Init( GPIO2, &CAN1_TX );
+
+ // Init 1 ms timebase
+ initTimebase2();
+
+ GPIO_WordWrite( GPIO0, 0x0000 ); // All LED's off
+
+ // * * * EIC * * *
+
+ // EIC Clock Enable
+ CFG_PeripheralClockConfig( CFG_CLK_EIC , ENABLE );
+
+ // EIC Config
+ EIC_IRQChannelPriorityConfig( RTC_IRQChannel, 1 );
+ EIC_IRQChannelPriorityConfig( TB2_IRQChannel, 2 );
+
+ //EIC_IRQChannelConfig( RTC_IRQChannel , ENABLE );
+
+
+ EIC_IRQCmd( ENABLE );
+
+ // * * * CMU * * *
+
+ // CMU Initialization
+ CMU_DeInit( );
+ CMU_StructInit(&CMU_InitStructure);
+
+ // Enable the external oscillator
+ CMU_InitStructure.CMU_CKSEL0 = CMU_CKSEL0_CKOSC;
+ CMU_Init(&CMU_InitStructure);
+
+ // Disable DIV2
+ PRCCU->CFR &= 0x7FFF;
+
+
+ // * * * RTC * * *
+
+ // Set RTC clock-------
+ // (clock:0-->9) fOSC=4Mhz/RTCP=(2,4,8,16,32,64,128,256,512,1024)
+ // -->EXTCLK=(4M,2M,1M,500K,250K,125K,62.5K,31.25K,15.625K,7.812K)
+
+
+ // RTC Clock Enable
+ CFG_PeripheralClockConfig( CFG_CLK_RTC , ENABLE );
+
+ // RTC Interrupt Config
+ RTC_ITConfig( RTC_IT_SEC | RTC_IT_ALA | RTC_IT_OV, ENABLE );
+
+ // RTC Configuration
+ RTC_InitStructure.RTC_Alarm = 6; // 0xFFFFFFFF;
+ RTC_InitStructure.RTC_Counter = 0; // 0xFFFFFFFA;
+ // configure RTC=1S ( RCK=1000000/64=CKL32=15625Hz )
+ // 8MHz/64 = 125000 = 0x1E848
+ RTC_InitStructure.RTC_Prescaler = 0x3D09; // == 15625
+ //RTC_InitStructure.RTC_Prescaler = 0x1E848; // 0x3D09; // == 15625
+
+ RTC_Init( &RTC_InitStructure );
+
+
+
+ // * * * CAN * * *
+ CAN_InitTypeDef CANInit = { 0x0, CAN_BITRATE_500K };
+
+ // initialize the CAN at a standard bitrate, interrupts disabled
+ CAN_Init( CAN0, &CANInit );
+
+ // configure the message objects
+ CAN_EnterInitMode( CAN0, CAN_CR_CCE );
+ CAN_InvalidateAllMsgObj( CAN0 );
+ CAN_SetTxMsgObj( CAN0, CAN0_TX_MSGOBJ, CAN_STD_ID );
+ CAN_SetRxMsgObj( CAN0, CAN0_RX_MSGOBJ, CAN_STD_ID, 0, CAN_LAST_STD_ID, TRUE );
+ CAN_LeaveInitMode( CAN0 );
+
+ GPIO_BitWrite( GPIO0, LD1, Bit_SET );
+
+ // * * * LCD * * *
+
+ // LCD Configuration
+ LCD_Init();
+ LCD_Clear();
+ //LCD_LineClear(1);
+ //LCD_LineClear(2);
+ LCD_SetPosCur(1,1);
+
+ // Display text message on LCD: Line 1
+ LCD_SendString( "SIMPLE CAN TEST", 1, 1 );
+ LCD_SetPosCur(2,1);
+
+
+ // * * * ADC * * *
+
+
+ // ADC Clock Enable
+ CFG_PeripheralClockConfig(CFG_CLK_ADC, ENABLE);
+
+ // ADC Configuration
+ ADC_DeInit ();
+ ADC_StructInit( &ADC_InitStructure );
+ ADC_InitStructure.ADC_Calibration = ADC_Calibration_ON;
+ ADC_InitStructure.ADC_CalibAverage = ADC_CalibAverage_Enable;
+ ADC_InitStructure.ADC_AutoClockOff = ADC_AutoClockOff_Disable ;
+ ADC_InitStructure.ADC_ConversionMode = ADC_ConversionMode_Scan ;
+ ADC_InitStructure.ADC_SamplingPrescaler = 0x2;
+ ADC_InitStructure.ADC_ConversionPrescaler = 0x4;
+ ADC_InitStructure.ADC_FirstChannel = ADC_CHANNEL0 ;
+ ADC_InitStructure.ADC_ChannelNumber = 1;
+ ADC_Init( &ADC_InitStructure );
+
+
+ // EOC interrupt Enable
+ ADC_ITConfig( ADC_IT_EOC, ENABLE );
+
+ // Enable ADC
+ ADC_Cmd( ENABLE );
+
+
+
+ while ( 1 ) {
+
+ // send a pre-defined data frame
+ CAN_SendMessage( CAN0, CAN0_TX_MSGOBJ, &TxCan0Msg[0] );
+
+ // wait until end of transmission
+ CAN_WaitEndOfTx( CAN0 );
+
+ // release the TX message object
+ CAN_ReleaseTxMessage( CAN0, CAN0_TX_MSGOBJ );
+
+ // Check for a data frame
+ if ( CAN_ReceiveMessage( CAN0, CAN0_RX_MSGOBJ, FALSE, &RxCan0Msg ) ) {
+
+ // Test Received Msg
+ if ( ( RxCan0Msg.IdType == CAN_STD_ID ) &&
+ ( RxCan0Msg.Id == 0x123) &&
+ ( RxCan0Msg.Dlc == 4 ) &&
+ ( RxCan0Msg.Data[ 0 ] == 0x01 ) &&
+ ( RxCan0Msg.Data[ 1 ] == 0x02 ) &&
+ ( RxCan0Msg.Data[ 2 ] == 0x04 ) &&
+ ( RxCan0Msg.Data[ 3 ] == 0x08 ) ){
+
+ // Received Msg OK
+ GPIO_BitWrite( GPIO0,LD15, Bit_SET ); // LED 15
+
+ LCD_SendString( "RECEIVE CAN MSG", 2, 1 );
+
+ }
+ else {
+
+ // Received some other Msg
+ GPIO_BitWrite( GPIO0, LD14, Bit_SET ); // LED 14
+
+ LCD_LineClear(2);
+
+ }
+
+ // Release the RX message object
+ CAN_ReleaseRxMessage(CAN0, CAN0_RX_MSGOBJ);
+
+ } // Received frame
+
+
+ // Start ADC conversion
+ ADC_ConversionCmd( ADC_ConversionStart );
+ buffer[8] = get1Digit( Conversion_Value );
+ buffer[7] = get10Digit( Conversion_Value );
+ buffer[6] = get100Digit( Conversion_Value );
+ buffer[5] = get1000Digit( Conversion_Value );
+ buffer[9] = 0;
+
+ // Display ADC conversion Value on LCD
+ //LCD_SendString( &buffer[5], 2, 5 );
+ CPIO_Value = 0;
+
+ for(u32 i = (u32)((float)Conversion_Value/60); i; i--) {
+ CPIO_Value <<= 1;
+ CPIO_Value |= 1;
+ }
+
+ GPIO_WordWrite( GPIO0, CPIO_Value );
+
+ // Wait for 500 ms
+ delay_ms( 500 );
+
+ } // while
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// get1000Digit
+//
+
+unsigned int get1000Digit( unsigned int val )
+{
+ return ( ( val / 1000 ) + 0x30 );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// get100Digit
+//
+
+unsigned int get100Digit( unsigned int val )
+{
+ unsigned int valCopy;
+ valCopy = val % 1000;
+ return ( (valCopy / 100 ) + 0x30 );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// get10Digit
+//
+
+unsigned int get10Digit( unsigned int val )
+{
+ unsigned int valCopy;
+ valCopy = val % 100;
+ return ( ( valCopy / 10 ) + 0x30 );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// get1Digit
+//
+
+unsigned int get1Digit( unsigned int val )
+{
+ unsigned int valCopy;
+ valCopy = val % 100;
+ return ( ( valCopy % 10 ) + 0x30 );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// wait
+//
+
+void wait( void )
+{
+ u32 i;
+
+ for (i=100000L; i!=0 ; i-- ) {}
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// MCLK_Config
+//
+
+void MCLK_Config (void)
+{
+
+ PRCCU_InitTypeDef Clock;
+ CMU_InitTypeDef ClockInit;
+
+ ClockInit.CMU_RCOscControl = 0x0D; // RC OSC Adjust
+ ClockInit.CMU_EndCountValue = 0x0F; //
+ ClockInit.CMU_FreqRef_High = 0xFF; //
+ ClockInit.CMU_FreqRef_Low = 0xFE; //
+
+ ClockInit.CMU_CKSEL0 = CMU_CKSEL0_CKOSC; // Clock for CLOCK1 (4MHz)
+ ClockInit.CMU_CKSEL1 = CMU_CKSEL1_CKPLL; // Clock for Freq. Meter (8MHz)
+ ClockInit.CMU_CKSEL2 = CMU_CKSEL2_CKOSC; // Clock to drive CMU logic
+
+ CMU_Lock( DISABLE );
+ CMU_Init( &ClockInit );
+
+ // Init. Power Reset Clock unit
+ // 4 MHz * 12 / 6 = 8 MHz = CLOCK2
+ Clock.PRCCU_DIV2 = DISABLE;
+ Clock.PRCCU_MCLKSRC_SRC = PRCCU_MCLKSRC_PLL; // Use PLL in
+ Clock.PRCCU_PLLDIV = PRCCU_PLLDIV_6;
+ Clock.PRCCU_PLLMUL = PRCCU_PLLMUL_12;
+
+ PRCCU_Init( &Clock );
+ PRCCU_SetExtClkDiv(4);
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// CAN0_Demo_Polling
+//
+
+void CAN0_Demo_Polling( void )
+{
+ CAN_InitTypeDef CANInit = { 0x0, CAN_BITRATE_500K };
+
+ // initialize the CAN at a standard bitrate, interrupts disabled
+ CAN_Init( CAN0, &CANInit );
+
+ // switch into Loopback+Silent mode (self-test)
+ //CAN_EnterTestMode( CAN0, CAN_TESTR_LBACK | 0 );
+
+ // configure the message objects
+ CAN_InvalidateAllMsgObj( CAN0 );
+ CAN_SetTxMsgObj( CAN0, CAN0_TX_MSGOBJ, CAN_STD_ID );
+ CAN_SetRxMsgObj( CAN0, CAN0_RX_MSGOBJ, CAN_STD_ID, 0, CAN_LAST_STD_ID, TRUE );
+
+ // send a pre-defined data frame
+ CAN_SendMessage( CAN0, CAN0_TX_MSGOBJ, &TxCan0Msg[0] );
+
+ // wait until end of transmission
+ CAN_WaitEndOfTx( CAN0 );
+
+ GPIO_BitWrite( GPIO0, LD16, Bit_SET ); // LED16;
+
+/*
+ // wait for reception of a data frame
+ while ( !CAN_ReceiveMessage( CAN0, CAN0_RX_MSGOBJ, FALSE, &RxCan0Msg ) ) {
+ // add a time-out handling here, if necessary
+ }
+
+ // Test Received Msg
+ if ( ( RxCan0Msg.IdType == CAN_STD_ID ) &&
+ ( RxCan0Msg.Id == 0x123) &&
+ ( RxCan0Msg.Dlc == 4 ) &&
+ ( RxCan0Msg.Data[ 0 ] == 0x01 ) &&
+ ( RxCan0Msg.Data[ 1 ] == 0x02 ) &&
+ ( RxCan0Msg.Data[ 2 ] == 0x04 ) &&
+ ( RxCan0Msg.Data[ 3 ] == 0x08 ) ){
+
+ // Received Msg OK
+ GPIO_BitWrite(GPIO0,LD1,Bit_SET);//LED1;
+ }
+ else {
+
+ // Received Msg OK
+ GPIO_BitWrite(GPIO0,LD2,Bit_RESET);//LED2 off;
+
+ }
+*/
+ // release the message objects
+ CAN_ReleaseTxMessage(CAN0, CAN0_TX_MSGOBJ);
+ CAN_ReleaseRxMessage(CAN0, CAN0_RX_MSGOBJ);
+
+ // switch back into Normal mode
+ //CAN_LeaveTestMode( CAN0 );
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// CAN0_Demo_Interrupt
+//
+
+void CAN0_Demo_Interrupt(void)
+{
+ CAN_InitTypeDef CAN0Init;
+ CAN0Init.CAN_Mask = CAN_CR_IE;
+ CAN0Init.CAN_Bitrate = CAN_BITRATE_100K;
+
+ // initialize the interrupt controller
+ EIC_IRQChannelConfig( CAN0_IRQChannel, ENABLE );
+ EIC_IRQChannelPriorityConfig( CAN0_IRQChannel, 1 );
+ EIC_IRQCmd( ENABLE );
+
+ // initialize the CAN at a standard bitrate, interrupts enabled
+ CAN_Init( CAN0, &CAN0Init );
+
+ // switch into Loopback+Silent mode (self-test)
+ CAN_EnterTestMode( CAN0, CAN_TESTR_LBACK | CAN_TESTR_SILENT );
+
+ // configure the message objects
+ CAN_InvalidateAllMsgObj( CAN0 );
+ CAN_SetTxMsgObj( CAN0, CAN0_TX_MSGOBJ, CAN_EXT_ID );
+ CAN_SetRxMsgObj( CAN0, CAN0_RX_MSGOBJ, CAN_EXT_ID, 0, CAN_LAST_EXT_ID, TRUE );
+
+ // send a pre-defined data frame
+ CAN_SendMessage( CAN0, CAN0_TX_MSGOBJ, &TxCan0Msg[1] );
+
+ // reception and release are done in the interrupt handler
+ wait();
+
+ GPIO_BitWrite(GPIO0,LD7,Bit_SET); // LED7
+
+ // switch back into Normal mode
+ CAN_LeaveTestMode( CAN0 );
+
+ // disable interrupts globally
+ EIC_IRQCmd( DISABLE );
+
+}
+
+
+
+/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/startup.s
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/startup.s (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/startup.s 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,361 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/**** Startup Code (executed after Reset) ****/
+
+/* Frequency values */
+/* set to suit target hardware */
+
+ .equ FOSC, 4000000
+ .equ FRTC, 2340000
+
+/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+
+ .equ Mode_USR, 0x10
+ .equ Mode_FIQ, 0x11
+ .equ Mode_IRQ, 0x12
+ .equ Mode_SVC, 0x13
+ .equ Mode_ABT, 0x17
+ .equ Mode_UND, 0x1B
+ .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
+
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
+
+/* --- System memory locations */
+
+ .equ EIC_Base_addr, 0xFFFFFC00 /* EIC base address */
+ .equ ICR_off_addr, 0x00 /* Interrupt Control register offset */
+ .equ CIPR_off_addr, 0x08 /* Current Interrupt Priority Register offset */
+ .equ IVR_off_addr, 0x18 /* Interrupt Vector Register offset */
+ .equ FIR_off_addr, 0x1C /* Fast Interrupt Register offset */
+ .equ IER0_off_addr, 0x20 /* Interrupt Enable Register offset */
+ .equ IER1_off_addr, 0x24 /* Interrupt Enable Register offset */
+ .equ IPR0_off_addr, 0x40 /* Interrupt Pending Bit Register offset */
+ .equ IPR1_off_addr, 0x44 /* Interrupt Pending Bit Register offset */
+ .equ SIR0_off_addr, 0x60 /* Source Interrupt Register 0 */
+
+ .equ CFG_R0_Addr, 0x40000000 /* Configuration Register 0 base address */
+ .equ CFG_PCGR0_Addr, 0x40000008
+
+ .equ FLASH_mask, 0x0000 /* to remap FLASH at 0x0 */
+ .equ RAM_mask, 0x0001 /* to remap RAM at 0x0 */
+
+/* define remapping, if using ram based vectors or rom based
+ REMAP will need to be define in vector.s aswell
+ Valid Options:
+ REMAP 0 - default config, no remapping, vectors in rom
+ REMAP 1 - vectors in rom
+ REMAP 2 - vectors in ram
+*/
+
+.ifndef REMAP
+ .equ REMAP, 0
+.endif
+
+/* if we are debugging in ram then we need
+ the vectors to point to the correct location
+ only if BOOT0/BOOT1 have been set for Flash @ zero.
+*/
+
+.ifndef DBGRAM
+ .equ DBGRAM, 0
+.endif
+
+/* Startup Code must be linked first at Address at which it expects to run. */
+
+ .text
+ .arm
+ .section .init, "ax"
+
+ .global _start
+ .global RCCU_Main_Osc
+ .global RCCU_RTC_Osc
+
+.if REMAP
+
+/* Exception Vector (before Remap) */
+
+/* Reset Handler */
+/* On reset, an aliased copy of ROM is at 0x0. */
+/* Continue execution from 'real' ROM rather than aliased copy */
+
+ LDR pc, =HardReset
+HardReset:
+
+/******************************************************************************
+REMAPPING
+Description : Remapping memory whether RAM,FLASH or External memory
+ at Address 0x0 after the application has started executing.
+ Remapping is generally done to allow RAM to replace FLASH
+ or EXTMEM at 0x0.
+ the remapping of RAM allow copying of vector table into RAM
+******************************************************************************/
+
+.if REMAP == 1
+ MOV r4, #FLASH_mask
+.endif
+
+.if REMAP == 2
+ MOV r4, #RAM_mask
+.endif
+
+remap:
+ LDR r1, =_vecstart /* r1 = start address from which to copy */
+ LDR r3, =_vecend
+ SUB r3, r3, r1 /* r3 = number of bytes to copy */
+ LDR r0, =_vectext /* r0 = start address where to copy */
+copy_ram:
+ LDR r2, [r0], #4 /* Read a word from the source */
+ STR r2, [r1], #4 /* copy the word to destination */
+ SUBS r3, r3, #4 /* Decrement number of words to copy */
+ BNE copy_ram
+
+ LDR r1, =CFG_R0_Addr
+ LDR r0, [r1]
+ BIC r0, r0, #0x01
+ ORR r0, r0, r4
+ STR r0, [r1]
+.endif
+
+/* After remap this will be our reset handler */
+
+_start:
+ LDR pc, =NextInst
+NextInst:
+
+ NOP /* Wait for OSC stabilization */
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+/* Reset all peripheral clocks except RAM */
+
+ MOV r0, #1
+ LDR r1, =CFG_PCGR0_Addr
+ STR r0, [r1]
+ MOV r0, #0
+ STR r0, [r1,#4]
+
+.if DBGRAM
+ LDR r1, =CFG_R0_Addr
+ LDR r0, [r1]
+ ORR r0, r0, #RAM_mask
+ STR r0, [r1]
+.endif
+
+/* Setup Stack for each mode */
+
+/* Enter Abort Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit
+ LDR sp, =__stack_abt_end__
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_UND|I_Bit|F_Bit
+ LDR sp, =__stack_und_end__
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit
+ LDR sp, =__stack_svc_end__
+
+/* Enter FIQ Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+ LDR sp, =__stack_fiq_end__
+
+/* Enter IRQ Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+ LDR sp, =__stack_irq_end__
+
+/* Enter System Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_SYS
+ LDR sp, =__stack_end__
+
+/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */
+ LDR sl, =__bss_end__
+
+/******************************************************************************
+EIC initialization
+Description : Initialize the EIC as following :
+ - IRQ disabled
+ - FIQ disabled
+ - IVR contain the load PC opcode (0xF59FF00)
+ - Current priority level equal to 0
+ - All channels are disabled
+ - All channels priority equal to 0
+ - All SIR registers contain offset to the related IRQ table entry
+******************************************************************************/
+
+/* enable eic clock */
+
+ LDR r1, =CFG_PCGR0_Addr
+ LDR r0, [r1]
+ ORR r0, r0, #0x20000000
+ STR r0, [r1]
+
+/* Wait for EIC stabilization */
+
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+EIC_INIT:
+ LDR r3, =EIC_Base_addr
+ LDR r4, =0x00000000
+ STR r4, [r3, #ICR_off_addr] /* Disable FIQ and IRQ */
+ STR r4, [r3, #IER0_off_addr] /* Disable all channels interrupts */
+ STR r4, [r3, #IER1_off_addr] /* Disable all channels interrupts */
+ LDR r4, =0xFFFFFFFF
+ STR r4, [r3, #IPR0_off_addr] /* Clear all IRQ pending bits */
+ STR r4, [r3, #IPR1_off_addr] /* Clear all IRQ pending bits */
+ LDR r4, =0x18
+ STR r4, [r3, #FIR_off_addr] /* Disable FIQ channels and clear FIQ pending bits */
+ LDR r4, =0x00000000
+ STR r4, [r3, #CIPR_off_addr] /* Reset the current priority register */
+ LDR r4, =0xE59F0000
+ STR r4, [r3, #IVR_off_addr] /* Write the LDR pc,pc,#offset instruction code in IVR[31:16] */
+ LDR r2, =64 /* 32 Channel to initialize */
+ LDR r0, =PRCCUCMU_Addr /* Read the address of the IRQs address table */
+ LDR r1, =0x00000FFF
+ AND r0, r0, r1
+ LDR r5, =SIR0_off_addr /* Read SIR0 address */
+ SUB r4, r0, #8 /* subtract 8 for prefetch */
+ LDR r1, =0xF3E8 /* add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000) */
+ /* 0xF7E8 used to complete the LDR pc,offset opcode */
+ ADD r1, r4, r1 /* compute the jump offset */
+EIC_INI:
+ MOV r4, r1, LSL #16 /* Left shift the result */
+ STR r4, [r3, r5] /* Store the result in SIRx register */
+ ADD r1, r1, #4 /* Next IRQ address */
+ ADD r5, r5, #4 /* Next SIR */
+ SUBS r2, r2, #1 /* Decrement the number of SIR registers to initialize */
+ BNE EIC_INI /* If more then continue */
+
+/* Relocate .data section (Copy from ROM to RAM) */
+ LDR r1, =_etext
+ LDR r2, =__data_start
+ LDR r3, =_edata
+LoopRel:
+ CMP r2, r3
+ LDRLO r0, [r1], #4
+ STRLO r0, [r2], #4
+ BLO LoopRel
+
+/* Clear .bss section (Zero init) */
+ MOV r0, #0
+ LDR r1, =__bss_start__
+ LDR r2, =__bss_end__
+LoopZI:
+ CMP r1, r2
+ STRLO r0, [r1], #4
+ BLO LoopZI
+
+/* Call C++ constructors */
+ LDR r0, =__ctors_start__
+ LDR r1, =__ctors_end__
+ctor_loop:
+ CMP r0, r1
+ BEQ ctor_end
+ LDR r2, [r0], #4
+ STMFD sp!, {r0-r1}
+ MOV lr, pc
+ BX r2
+ LDMFD sp!, {r0-r1}
+ B ctor_loop
+ctor_end:
+
+/* Need to set up standard file handles */
+/* Only used under simulator, normally overide syscall.c */
+# BL initialise_monitor_handles
+
+/* if we use debug version of str7lib this will call the init function */
+
+ BL libdebug
+libdebug:
+
+/* Enter the C code, use B instruction so as to never return */
+/* use BL main if you want to use c++ destructors below */
+ B main
+
+/* Call destructors */
+# LDR r0, =__dtors_start__
+# LDR r1, =__dtors_end__
+dtor_loop:
+# CMP r0, r1
+# BEQ dtor_end
+# LDR r2, [r0], #4
+# STMFD sp!, {r0-r1}
+# MOV lr, pc
+# BX r2
+# LDMFD sp!, {r0-r1}
+# B dtor_loop
+dtor_end:
+
+/* Return from main, loop forever. */
+exit_loop:
+# B exit_loop
+
+/* Disable the ARM7 core IRQ line */
+ARMIRQ_Disable:
+ MRS r0, CPSR
+ ORR r0, r0, #I_Bit
+ MSR CPSR_c, r0
+ BX lr
+
+/* Disable the ARM7 core FIQ line. */
+ARMFIQ_Disable:
+ MRS r0, CPSR
+ ORR r0, r0, #F_Bit
+ MSR CPSR_c, r0
+ BX lr
+
+/* Enable the ARM7 core IRQ line. */
+ARMIRQ_Enable:
+ MRS r0, CPSR
+ BIC r0, r0,#I_Bit
+ MSR CPSR_c, r0
+ BX lr
+
+/* Enable the ARM7 core FIQ line. */
+ARMFIQ_Enable:
+ MRS r0, CPSR
+ BIC r0, r0,#F_Bit
+ MSR CPSR_c, r0
+ BX lr
+
+ .global ARMIRQ_Enable
+ .global ARMFIQ_Enable
+ .global ARMIRQ_Disable
+ .global ARMFIQ_Disable
+
+/* Fosc values, used by libstr7 */
+
+RCCU_Main_Osc: .long FOSC
+RCCU_RTC_Osc: .long FRTC
+
+ .weak libdebug
+
+ .end
Added: trunk/firmware/arm/str/vscp_node_str73x_gcc/vector.s
===================================================================
--- trunk/firmware/arm/str/vscp_node_str73x_gcc/vector.s (rev 0)
+++ trunk/firmware/arm/str/vscp_node_str73x_gcc/vector.s 2008-02-11 17:33:26 UTC (rev 837)
@@ -0,0 +1,1189 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+ .equ EIC_base_addr, 0xFFFFFC00 /* EIC base address. */
+ .equ CICR_off_addr, 0x04 /* Current Interrupt Channel Register. */
+ .equ IVR_off_addr, 0x18 /* Interrupt Vector Register. */
+ .equ IPR0_off_addr, 0x40 /* Interrupt Pending Register. */
+ .equ IPR1_off_addr, 0x44 /* Interrupt Pending Register. */
+
+ /* set HIRAM 1 for Interrupt Handlers reside in ram Vectors in ram uses 192 bytes
+ Vectors/Handlers uses 1452 bytes, normally 0 */
+
+.ifndef HIRAM
+ .equ HIRAM, 0
+.endif
+
+.ifndef REMAP
+ .equ REMAP, 0
+.endif
+
+ .text
+ .arm
+
+.if REMAP > 1
+ .section .vectram, "ax"
+.else
+ .section .vectrom, "ax"
+.endif
+
+ .global PRCCUCMU_Addr
+ .global Reset_Vec
+
+/* Note: LDR PC instructions are used here, though branch (B) instructions */
+/* could also be used, unless the ROM is at an address >32MB. */
+
+/*******************************************************************************
+ Exception vectors
+*******************************************************************************/
+
+Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */
+Undef_Vec: LDR pc, Undefined_Addr
+SWI_Vec: LDR pc, SWI_Addr
+PAbt_Vec: LDR pc, Prefetch_Addr
+DAbt_Vec: LDR pc, Abort_Addr
+ NOP /* Reserved vector */
+IRQ_Vec: LDR pc, IRQ_Addr
+FIQ_Vec: LDR pc, FIQ_Addr
+
+/*******************************************************************************
+ Exception handlers address table
+*******************************************************************************/
+
+Reset_Addr: .word _start
+Undefined_Addr: .word UndefinedHandler
+SWI_Addr: .word SWIHandler
+Prefetch_Addr: .word PrefetchHandler
+Abort_Addr: .word AbortHandler
+ ...
[truncated message content] |
