Menu
▾
▴
[Can-svn] SF.net SVN: can: [829] trunk/firmware/arm/str
|
From: <ak...@us...> - 2008-02-06 13:07:09
|
Revision: 829
http://can.svn.sourceforge.net/can/?rev=829&view=rev
Author: akhe
Date: 2008-02-06 05:07:08 -0800 (Wed, 06 Feb 2008)
Log Message:
-----------
Added templates for all STR7 uP's
Added Paths:
-----------
trunk/firmware/arm/str/template72x/
trunk/firmware/arm/str/template72x/Makefile
trunk/firmware/arm/str/template72x/STR72x-RAM.ld
trunk/firmware/arm/str/template72x/STR72x-ROM.ld
trunk/firmware/arm/str/template72x/main.c
trunk/firmware/arm/str/template72x/startup.s
trunk/firmware/arm/str/template72x/vector.s
trunk/firmware/arm/str/template72x/vectors.c
trunk/firmware/arm/str/template72x/vectors.h
Added: trunk/firmware/arm/str/template72x/Makefile
===================================================================
--- trunk/firmware/arm/str/template72x/Makefile (rev 0)
+++ trunk/firmware/arm/str/template72x/Makefile 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,495 @@
+# Hey Emacs, this is a -*- makefile -*-
+#
+# WinARM template makefile
+# by Giacomo Fazio and Antonio Nasca, Catania, Italy
+# <gia...@gm...>
+# <ant...@ho...>
+#
+# based on the WinARM template makefile written by Martin Thomas
+# Released to the Public Domain
+# Please read the make user manual!
+#
+#
+# On command line:
+#
+# make all = Make software.
+#
+# make clean = Clean out built project files.
+#
+# make program = Download the hex file to the device
+#
+# (TODO: make filename.s = Just compile filename.c into the assembler code only)
+#
+# To rebuild project do "make clean" then "make all".
+# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe)
+TCHAIN = arm-elf
+#TCHAIN = arm-none-eabi
+
+#USE_THUMB_MODE = YES
+USE_THUMB_MODE = NO
+
+# MCU name and submodel
+MCU = arm7tdmi
+SUBMDL = STR72x
+
+## Create ROM-Image
+#RUN_MODE=ROM_RUN
+## Create RAM-Image
+RUN_MODE=RAM_RUN
+
+## not supported in this example:
+## Exception-Vector placement only supported for "ROM_RUN"
+## (placement settings ignored when using "RAM_RUN")
+## - Exception vectors in ROM:
+#VECTOR_LOCATION=VECTORS_IN_ROM
+## - Exception vectors in RAM:
+#VECTOR_LOCATION=VECTORS_IN_RAM
+
+
+# Target file name (without extension).
+TARGET = main
+
+# List C source files here. (C dependencies are automatically generated.)
+# use file-extension c for "c-only"-files
+SRC = src/$(TARGET).c
+
+# List C source files here which must be compiled in ARM-Mode.
+# use file-extension c for "c-only"-files
+SRCARM = src/vectors.c
+# thumb is possible too for vectors.c - keep ARM, TODO: profile
+
+# List C++ source files here.
+# use file-extension cpp for C++-files (use extension .cpp)
+CPPSRC =
+
+# List C++ source files here which must be compiled in ARM-Mode.
+# use file-extension cpp for C++-files (use extension .cpp)
+#CPPSRCARM = $(TARGET).cpp
+CPPSRCARM =
+
+# List Assembler source files here.
+# Make them always end in a capital .S. Files ending in a lowercase .s
+# will not be considered source files but generated files (assembler
+# output from the compiler), and will be deleted upon "make clean"!
+# Even though the DOS/Win* filesystem matches both .s and .S the same,
+# it will preserve the spelling of the filenames, and gcc itself does
+# care about how the name is spelled on its command-line.
+ASRC =
+
+# List Assembler source files here which must be assembled in ARM-Mode..
+ASRCARM = src/vector.S src/startup.S
+
+# Path to Linker-Scripts
+LINKERSCRIPTPATH = .
+
+## Output format. (can be ihex or binary or both)
+## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision)
+#FORMAT = ihex
+#FORMAT = binary
+FORMAT = both
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+#OPT = s
+OPT = 0
+
+## Using the Atmel AT91_lib produces warning with
+## the default warning-levels.
+## yes - disable these warnings; no - keep default settings
+#AT91LIBNOWARN = yes
+AT91LIBNOWARN = no
+
+# Debugging format.
+# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2.
+# AVR (extended) COFF requires stabs, plus an avr-objcopy run.
+#DEBUG = stabs
+DEBUG = dwarf-2
+
+# List any extra directories to look for include files here.
+# Each directory must be seperated by a space.
+EXTRAINCDIRS = ./include ./str72x_lib/include
+
+# List any extra directories to look for library files here.
+# Each directory must be seperated by a space.
+#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4
+EXTRA_LIBDIRS = ./str72x_lib
+
+
+# Compiler flag to set the C Standard level.
+# c89 - "ANSI" C
+# gnu89 - c89 plus GCC extensions
+# c99 - ISO C99 standard (not yet fully implemented)
+# gnu99 - c99 plus GCC extensions
+CSTANDARD = -std=gnu99
+
+# Place -D or -U options for C here
+CDEFS = -D$(RUN_MODE)
+
+# Place -I options here
+CINCS =
+
+# Place -D or -U options for ASM here
+ADEFS = -D$(RUN_MODE)
+
+ifdef VECTOR_LOCATION
+CDEFS += -D$(VECTOR_LOCATION)
+ADEFS += -D$(VECTOR_LOCATION)
+endif
+
+CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+
+# Compiler flags.
+
+ifeq ($(USE_THUMB_MODE),YES)
+THUMB = -mthumb
+THUMB_IW = -mthumb-interwork
+else
+THUMB =
+THUMB_IW =
+endif
+
+# -g*: generate debugging information
+# -O*: optimization level
+# -f...: tuning, see GCC manual and avr-libc documentation
+# -Wall...: warning level
+# -Wa,...: tell GCC to pass this to the assembler.
+# -adhlns...: create assembler listing
+#
+# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
+CFLAGS = -g$(DEBUG)
+CFLAGS += $(CDEFS) $(CINCS)
+CFLAGS += -O$(OPT)
+CFLAGS += -Wall -Wcast-align -Wimplicit
+CFLAGS += -Wpointer-arith -Wswitch
+CFLAGS += -ffunction-sections -fdata-sections
+CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused
+CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<)
+CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+
+# flags only for C
+CONLYFLAGS += -Wnested-externs
+CONLYFLAGS += $(CSTANDARD)
+
+ifneq ($(AT91LIBNOWARN),yes)
+#AT91-lib warnings with:
+CFLAGS += -Wcast-qual
+CONLYFLAGS += -Wmissing-prototypes
+CONLYFLAGS += -Wstrict-prototypes
+CONLYFLAGS += -Wmissing-declarations
+endif
+
+# flags only for C++ (arm-elf-g++)
+# CPPFLAGS = -fno-rtti -fno-exceptions
+CPPFLAGS =
+
+# Assembler flags.
+# -Wa,...: tell GCC to pass this to the assembler.
+# -ahlns: create listing
+# -g$(DEBUG): have the assembler create line number information
+ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG)
+
+
+#Additional libraries.
+
+# Extra libraries
+# Each library-name must be seperated by a space.
+# To add libxyz.a, libabc.a and libefsl.a:
+# EXTRA_LIBS = xyz abc efsl
+#EXTRA_LIBS = efsl
+EXTRA_LIBS = STR72x_lib
+
+#Support for newlibc-lpc (file: libnewlibc-lpc.a)
+#NEWLIBLPC = -lnewlib-lpc
+
+MATH_LIB = -lm
+
+# CPLUSPLUS_LIB = -lstdc++
+
+
+# Linker flags.
+# -Wl,...: tell GCC to pass this to linker.
+# -Map: create map file
+# --cref: add cross reference to map file
+LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections
+LDFLAGS += -lc
+LDFLAGS += $(NEWLIBLPC) $(MATH_LIB)
+LDFLAGS += -lc -lgcc
+LDFLAGS += $(CPLUSPLUS_LIB)
+LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS))
+LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS))
+
+# Set Linker-Script Depending On Selected Memory and Controller
+ifeq ($(RUN_MODE),RAM_RUN)
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld
+else
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld
+endif
+
+
+# Define directories, if needed.
+## DIRARM = c:/WinARM/
+## DIRARMBIN = $(DIRAVR)/bin/
+## DIRAVRUTILS = $(DIRAVR)/utils/bin/
+
+# Define programs and commands.
+SHELL = sh
+CC = $(TCHAIN)-gcc
+CPP = $(TCHAIN)-g++
+AR = $(TCHAIN)-ar
+OBJCOPY = $(TCHAIN)-objcopy
+OBJDUMP = $(TCHAIN)-objdump
+SIZE = $(TCHAIN)-size
+NM = $(TCHAIN)-nm
+REMOVE = rm -f
+REMOVEDIR = rm -f -r
+COPY = cp
+
+# Define Messages
+# English
+MSG_ERRORS_NONE = Errors: none
+MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------"
+MSG_END = -------- end --------
+MSG_SIZE_BEFORE = Size before:
+MSG_SIZE_AFTER = Size after:
+MSG_FLASH = Creating load file for Flash:
+MSG_EXTENDED_LISTING = Creating Extended Listing:
+MSG_SYMBOL_TABLE = Creating Symbol Table:
+MSG_LINKING = Linking:
+MSG_COMPILING = Compiling C:
+MSG_COMPILING_ARM = "Compiling C (ARM-only):"
+MSG_COMPILINGCPP = Compiling C++:
+MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):"
+MSG_ASSEMBLING = Assembling:
+MSG_ASSEMBLING_ARM = "Assembling (ARM-only):"
+MSG_CLEANING = Cleaning project:
+MSG_FORMATERROR = Can not handle output-format
+MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now.
+
+# Define all object files.
+COBJ = $(SRC:.c=.o)
+AOBJ = $(ASRC:.S=.o)
+COBJARM = $(SRCARM:.c=.o)
+AOBJARM = $(ASRCARM:.S=.o)
+CPPOBJ = $(CPPSRC:.cpp=.o)
+CPPOBJARM = $(CPPSRCARM:.cpp=.o)
+
+# Define all listing files.
+LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst)
+LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst)
+
+# Compiler flags to generate dependency files.
+### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d
+GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d
+
+# Combine all necessary flags and optional flags.
+# Add target processor to flags.
+ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS)
+ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS)
+
+
+# Default target.
+all: begin gccversion sizebefore build sizeafter finished end
+
+ifeq ($(FORMAT),ihex)
+build: elf hex lss sym
+hex: $(TARGET).hex
+IMGEXT=hex
+else
+ifeq ($(FORMAT),binary)
+build: elf bin lss sym
+bin: $(TARGET).bin
+IMGEXT=bin
+else
+ifeq ($(FORMAT),both)
+build: elf hex bin lss sym
+hex: $(TARGET).hex
+bin: $(TARGET).bin
+else
+$(error "$(MSG_FORMATERROR) $(FORMAT)")
+endif
+endif
+endif
+
+elf: $(TARGET).elf
+lss: $(TARGET).lss
+sym: $(TARGET).sym
+
+# Eye candy.
+begin:
+ @echo
+ @echo $(MSG_BEGIN)
+
+finished:
+ @echo $(MSG_ERRORS_NONE)
+
+end:
+ @echo $(MSG_END)
+ @echo
+
+
+# Display size of file.
+HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
+ELFSIZE = $(SIZE) -A $(TARGET).elf
+sizebefore:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi
+
+sizeafter:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi
+
+
+# Display compiler version information.
+gccversion :
+ @$(CC) --version
+
+# FLASH Programming with OPENOCD
+
+# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe)
+# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded
+OPENOCD_DIR = 'c:\Programmi\openocd\bin\'
+
+# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger)
+OPENOCD = $(OPENOCD_DIR)openocd-pp.exe
+#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe
+
+# specify OpenOCD configuration file (pick the one for your device)
+#OPENOCD_CFG = C:\openocd-configs\str72x-configs\str72x_signalyzer-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str72x-configs\str72x_jtagkey-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str72x-configs\str72x_armusbocd-flash-program.cfg
+OPENOCD_CFG = C:\openocd-configs\str72x-configs\str72x_pp-flash-program.cfg
+
+program:
+ @echo
+ @echo "Flash Programming with OpenOCD..."
+ $(OPENOCD) -f $(OPENOCD_CFG)
+ @echo
+ @echo
+ @echo "Flash Programming Finished."
+
+
+# Create final output file (.hex) from ELF output file.
+%.hex: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O ihex $< $@
+
+# Create final output file (.bin) from ELF output file.
+%.bin: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O binary $< $@
+
+
+# Create extended listing file from ELF output file.
+# testing: option -C
+%.lss: %.elf
+ @echo
+ @echo $(MSG_EXTENDED_LISTING) $@
+ $(OBJDUMP) -h -S -C $< > $@
+
+
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+ @echo
+ @echo $(MSG_SYMBOL_TABLE) $@
+ $(NM) -n $< > $@
+
+
+# Link: create ELF output file from object files.
+.SECONDARY : $(TARGET).elf
+.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+ @echo
+ @echo $(MSG_LINKING) $@
+ $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+
+# Compile: create object files from C source files. ARM/Thumb
+$(COBJ) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING) $<
+ $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C source files. ARM-only
+$(COBJARM) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING_ARM) $<
+ $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM/Thumb
+$(CPPOBJ) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP) $<
+ $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM-only
+$(CPPOBJARM) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP_ARM) $<
+ $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C source files. ARM/Thumb
+## does not work - TODO - hints welcome
+##$(COBJ) : %.s : %.c
+## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM/Thumb
+$(AOBJ) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING) $<
+ $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM-only
+$(AOBJARM) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING_ARM) $<
+ $(CC) -c $(ALL_ASFLAGS) $< -o $@
+
+
+# Target: clean project.
+clean: begin clean_list finished end
+
+
+clean_list :
+ @echo
+ @echo $(MSG_CLEANING)
+ $(REMOVE) $(TARGET).hex
+ $(REMOVE) $(TARGET).bin
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).elf
+ $(REMOVE) $(TARGET).map
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).a90
+ $(REMOVE) $(TARGET).sym
+ $(REMOVE) $(TARGET).lnk
+ $(REMOVE) $(TARGET).lss
+ $(REMOVE) $(COBJ)
+ $(REMOVE) $(CPPOBJ)
+ $(REMOVE) $(AOBJ)
+ $(REMOVE) $(COBJARM)
+ $(REMOVE) $(CPPOBJARM)
+ $(REMOVE) $(AOBJARM)
+ $(REMOVE) $(LST)
+ $(REMOVE) $(SRC:.c=.s)
+ $(REMOVE) $(SRC:.c=.d)
+ $(REMOVE) $(SRCARM:.c=.s)
+ $(REMOVE) $(SRCARM:.c=.d)
+ $(REMOVE) $(CPPSRC:.cpp=.s)
+ $(REMOVE) $(CPPSRC:.cpp=.d)
+ $(REMOVE) $(CPPSRCARM:.cpp=.s)
+ $(REMOVE) $(CPPSRCARM:.cpp=.d)
+ $(REMOVEDIR) .dep | exit 0
+
+
+# Include the dependency files.
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+
+# Listing of phony targets.
+.PHONY : all begin finish end sizebefore sizeafter gccversion \
+build elf hex bin lss sym clean clean_list program
+
Added: trunk/firmware/arm/str/template72x/STR72x-RAM.ld
===================================================================
--- trunk/firmware/arm/str/template72x/STR72x-RAM.ld (rev 0)
+++ trunk/firmware/arm/str/template72x/STR72x-RAM.ld 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,219 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/* Memory Definitions */
+
+MEMORY
+{
+ DATA (rw) : ORIGIN = 0x60000000, LENGTH = 0x00004000
+ SDRAM (rw) : ORIGIN = 0xA0000000, LENGTH = 0x00100000
+}
+
+/* Section Definitions */
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+
+ .text :
+ {
+ KEEP(*(.vectrom))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t .glue_7)
+ KEEP(*(.fini))
+ *(.gcc_except_table)
+ } >SDRAM =0
+ . = ALIGN(4);
+
+ /* .ctors .dtors are used for c++ constructors/destructors */
+
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ } >SDRAM
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ } >SDRAM
+
+ /* .rodata section which is used for read-only data (constants) */
+
+ .rodata :
+ {
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >SDRAM
+ . = ALIGN(4);
+
+ _vectext = .;
+ PROVIDE (vectext = .);
+
+ .vect : AT (_vectext)
+ {
+ _vecstart = .;
+ KEEP(*(.vectram))
+ _vecend = .;
+ } >DATA
+
+ _etext = _vectext + SIZEOF(.vect);
+ PROVIDE (etext = .);
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_etext)
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ } >DATA
+ . = ALIGN(4);
+
+ __data_start = .;
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* .bss section which is used for uninitialized data */
+
+ .bss :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >DATA
+ . = ALIGN(4);
+ __bss_end__ = .;
+
+ _end = .;
+ PROVIDE(end = .);
+
+ /* .heap section (2048 bytes) which is used for memory allocation */
+
+ .heap (NOLOAD) :
+ {
+ __heap_start__ = .;
+ *(.heap)
+ . = MAX(__heap_start__ + 2048, .);
+ } >DATA
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ /* .stack section (2048 bytes) - user mode stack */
+
+ .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_start__ = .;
+ *(.stack)
+ . = MAX(__stack_start__ + 2048, .);
+ } >DATA
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ /* .stack_irq section (1024 bytes) */
+
+ .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq)
+ . = MAX(__stack_irq_start__ + 1024, .);
+ } >DATA
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ /* .stack_fiq section (256 bytes) */
+
+ .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq)
+ . = MAX(__stack_fiq_start__ + 256, .);
+ } >DATA
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ /* .stack_svc section (256 bytes) */
+
+ .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc)
+ . = MAX(__stack_svc_start__ + 256, .);
+ } >DATA
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ /* .stack_abt section (256 bytes) */
+
+ .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt)
+ . = MAX(__stack_abt_start__ + 256, .);
+ } >DATA
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ /* .stack_und section (256 bytes) */
+
+ .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_und_start__ = .;
+ *(.stack_und)
+ . = MAX(__stack_und_start__ + 256, .);
+ } >DATA
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
Added: trunk/firmware/arm/str/template72x/STR72x-ROM.ld
===================================================================
--- trunk/firmware/arm/str/template72x/STR72x-ROM.ld (rev 0)
+++ trunk/firmware/arm/str/template72x/STR72x-ROM.ld 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,221 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/* Memory Definitions */
+
+MEMORY
+{
+ BOOT (rx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+ CODE (rx) : ORIGIN = 0x40000000, LENGTH = 0x00400000
+ DATA (rw) : ORIGIN = 0x60000000, LENGTH = 0x00004000
+ SDRAM (rw) : ORIGIN = 0xA0000000, LENGTH = 0x00100000
+}
+
+/* Section Definitions */
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+
+ .text :
+ {
+ KEEP(*(.vectrom))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t .glue_7)
+ KEEP(*(.fini))
+ *(.gcc_except_table)
+ } >CODE =0
+ . = ALIGN(4);
+
+ /* .ctors .dtors are used for c++ constructors/destructors */
+
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ } >CODE
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ } >CODE
+
+ /* .rodata section which is used for read-only data (constants) */
+
+ .rodata :
+ {
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >CODE
+ . = ALIGN(4);
+
+ _vectext = .;
+ PROVIDE (vectext = .);
+
+ .vect : AT (_vectext)
+ {
+ _vecstart = .;
+ KEEP(*(.vectram))
+ _vecend = .;
+ } >DATA
+
+ _etext = _vectext + SIZEOF(.vect);
+ PROVIDE (etext = .);
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_etext)
+ {
+ __data_start = .;
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ } >DATA
+ . = ALIGN(4);
+
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* .bss section which is used for uninitialized data */
+
+ .bss :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >DATA
+ . = ALIGN(4);
+ __bss_end__ = .;
+
+ _end = .;
+ PROVIDE(end = .);
+
+ /* .heap section (2048 bytes) which is used for memory allocation */
+
+ .heap (NOLOAD) :
+ {
+ __heap_start__ = .;
+ *(.heap)
+ . = MAX(__heap_start__ + 2048, .);
+ } >DATA
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ /* .stack section (2048 bytes) - user mode stack */
+
+ .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_start__ = .;
+ *(.stack)
+ . = MAX(__stack_start__ + 2048, .);
+ } >DATA
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ /* .stack_irq section (1024 bytes) */
+
+ .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq)
+ . = MAX(__stack_irq_start__ + 1024, .);
+ } >DATA
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ /* .stack_fiq section (256 bytes) */
+
+ .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq)
+ . = MAX(__stack_fiq_start__ + 256, .);
+ } >DATA
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ /* .stack_svc section (256 bytes) */
+
+ .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc)
+ . = MAX(__stack_svc_start__ + 256, .);
+ } >DATA
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ /* .stack_abt section (32 bytes) */
+
+ .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt)
+ . = MAX(__stack_abt_start__ + 32, .);
+ } >DATA
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ /* .stack_und section (32 bytes) */
+
+ .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_und_start__ = .;
+ *(.stack_und)
+ . = MAX(__stack_und_start__ + 32, .);
+ } >DATA
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
Added: trunk/firmware/arm/str/template72x/main.c
===================================================================
--- trunk/firmware/arm/str/template72x/main.c (rev 0)
+++ trunk/firmware/arm/str/template72x/main.c 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,43 @@
+/******************** (C) COPYRIGHT 2005 STMicroelectronics ********************
+* File Name : main.c
+* Author : MCD Application Team
+* Date First Issued : 09/27/2005 : V1.0
+* Description : Main program body
+**********************************************************************************
+* History:
+* 09/27/2005 : V1.0
+**********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*********************************************************************************/
+
+/* Standard include ------------------------------------------------------------*/
+#include "720_lib.h"
+
+/* Include of other module interface headers -----------------------------------*/
+/* Local includes --------------------------------------------------------------*/
+/* Private typedef -------------------------------------------------------------*/
+/* Private define --------------------------------------------------------------*/
+/* Private macro ---------------------------------------------------------------*/
+/* Private variables -----------------------------------------------------------*/
+
+
+/*---------------------------------main---------------------------------------*/
+
+void main()
+{
+ #ifdef LIBDEBUG
+ libdebug();
+ #endif
+ int a=4;
+ int b=5;
+ int c;
+ c=a+b;
+}
+
+
+/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/
Added: trunk/firmware/arm/str/template72x/startup.s
===================================================================
--- trunk/firmware/arm/str/template72x/startup.s (rev 0)
+++ trunk/firmware/arm/str/template72x/startup.s 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,464 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/***********************************************************************************
+* This Module gives also a simple example of MMU & CACHE
+* setup according to the STR720-EVAL (MB397) board memory mapping
+* and can be customized to user application needs.
+***********************************************************************************/
+
+/**** Startup Code (executed after Reset) ****/
+
+/* Frequency values */
+/* set to suit target hardware */
+
+ .equ FOSC, 16000000
+
+/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+
+ .equ Mode_USR, 0x10
+ .equ Mode_FIQ, 0x11
+ .equ Mode_IRQ, 0x12
+ .equ Mode_SVC, 0x13
+ .equ Mode_ABT, 0x17
+ .equ Mode_UND, 0x1B
+ .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
+
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
+
+/* --- System memory locations */
+
+ .equ EIC_Base_addr, 0xFFFFFC00 /* EIC base address */
+ .equ ICR_off_addr, 0x00 /* Interrupt Control register offset */
+ .equ CIPR_off_addr, 0x08 /* Current Interrupt Priority Register offset */
+ .equ IVR_off_addr, 0x18 /* Interrupt Vector Register offset */
+ .equ FIR_off_addr, 0x1C /* Fast Interrupt Register offset */
+ .equ IER_off_addr, 0x20 /* Interrupt Enable Register offset */
+ .equ IPR_off_addr, 0x40 /* Interrupt Pending Bit Register offset */
+ .equ SIR0_off_addr, 0x60 /* Source Interrupt Register 0 */
+
+ .equ DRAMC_off_addr, 0xF0000000 /* DRAMC base address */
+ .equ SGCR1_off_addr, 0xF0000C00 /* S-APB Global Configuration Register 1 */
+ .equ CGCPCG_off_addr, 0xF0002C00 /* CGC Peripheral Clock Gating Register 1 */
+
+# DRAMC Registers Offsets
+
+ .equ MB1Config, 0x00
+ .equ SDRAM1ConfigLo, 0x10
+ .equ SDRAM1ConfigHi, 0x14
+ .equ MEMConfig, 0x30
+ .equ Bank1Size, 0x34
+
+# SDRAM Commands
+
+ .equ DRAMC_NOP, 0x0 /* No operation */
+ .equ DRAMC_ACT, 0x1 /* Bank active */
+ .equ DRAMC_READ, 0x2 /* Read */
+ .equ DRAMC_CBR, 0x3 /* Auto refresh */
+ .equ DRAMC_BST, 0x4 /* Burst stop */
+ .equ DRAMC_PRECH, 0x5 /* Precharge selected */
+ .equ DRAMC_WRITE, 0x6 /* Write */
+ .equ DRAMC_MRS, 0x7 /* Mode register set */
+
+# MMU & CACHE Defines
+
+ .equ Fault, 0x000
+ .equ Section, 0x002
+ .equ B, 0x004 /* Bufferable */
+ .equ C, 0x008 /* Cachable */
+ .equ TTBit, 0x010
+ .equ Domain, 0x1E0
+ .equ FullAccess, 0xC00
+
+.ifndef REMAP
+ .equ REMAP, 0
+.endif
+
+/* Startup Code must be linked first at Address at which it expects to run. */
+
+ .text
+ .arm
+ .section .init, "ax"
+
+ .global _start
+ .global RCCU_Main_Osc
+ .global Cache_Enable
+ .global Cache_Disable
+
+_start:
+ LDR pc, =NextInst
+NextInst:
+ NOP /* Wait for OSC stabilization */
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+# Perform EMI/RAM remapping, if required
+# On reset, an aliased copy of EMI (@0x40000000) is at 0x0.
+# Continue execution from 'real' EMI memory rather than aliased copy
+
+.if REMAP >= 2
+ LDR r1, =SGCR1_off_addr
+ LDR r0, [r1]
+ ORR r0, r0, #0x1
+ STR r0, [r1]
+
+ LDR r1, =_vecstart /* r1 = start address from which to copy */
+ LDR r3, =_vecend
+ SUB r3, r3, r1 /* r3 = number of bytes to copy */
+ LDR r0, =_vectext /* r0 = start address where to copy */
+copy_ram:
+ LDR r2, [r0], #4 /* Read a word from the source */
+ STR r2, [r1], #4 /* copy the word to destination */
+ SUBS r3, r3, #4 /* Decrement number of words to copy */
+ BNE copy_ram
+.endif
+
+/* Setup Stack for each mode */
+
+/* Enter Abort Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit
+ LDR sp, =__stack_abt_end__
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_UND|I_Bit|F_Bit
+ LDR sp, =__stack_und_end__
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit
+ LDR sp, =__stack_svc_end__
+
+/* Enter FIQ Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+ LDR sp, =__stack_fiq_end__
+
+/* Enter IRQ Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+ LDR sp, =__stack_irq_end__
+
+/* Enter System Mode and set its Stack Pointer */
+ MSR cpsr_c, #Mode_SYS
+ LDR sp, =__stack_end__
+
+/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */
+ LDR sl, =__bss_end__
+
+# Initialize critical IO devices
+# The following devices are initialized (DRAMC/MMU/EIC)
+
+/* DRAMC initialization */
+/***********************************************************************************
+Description : Initialize the DRAMC :
+ - Enter POWERSAVE.
+ - Configure SDRAM and exit power save mode.
+ - Precharge all the banks.
+ - Execute the auto refresh command at least eight times.
+ - Execute the mode register set command to initialize
+ the mode register.
+***********************************************************************************/
+
+# Configure SDRAM Controller
+# Enter POWERSAVE
+# Type : SDRAM
+# Only Block 1 enabled
+# Refresh period: 16
+ LDR r0, =DRAMC_off_addr
+ LDR r1, =0x3130
+ STR r1, [r0, #MEMConfig]
+# BANK 1 configuration
+# ---------------------------------------------
+# Data width : WORD
+# Data latency : 3 cycles
+# Setup time : 0
+# Idle time : 0
+# Col. width : 8 bit
+# Size : 16 Mb
+ LDR r1, =0x0B00 /* Bank1 configuration */
+ STR r1, [r0, #MB1Config]
+ LDR r1, =0x00FF /* Bank1 size */
+ STR r1, [r0, #Bank1Size]
+
+# Configure SDRAM device
+ LDR r1, =0x1130
+ STR r1, [r0, #MEMConfig] /* Exit POWERSAVE */
+
+# Precharge all banks PALL (enter idle state)
+ LDR r1, =0x0400 /* Bit 10 set stands for all banks */
+ STR r1, [r0, #SDRAM1ConfigLo]
+ MOV r1, #DRAMC_PRECH
+ STR r1, [r0, #SDRAM1ConfigHi]
+
+# Issue 8 auto-refresh commands (CBR) to complete power-up sequence
+ MOV r1, #DRAMC_CBR
+ STR r1, [r0, #SDRAM1ConfigHi] /* Low part of configuration data is not required */
+ STR r1, [r0, #SDRAM1ConfigHi] /* Distance between CBRs must be greater than 70 ns */
+ STR r1, [r0, #SDRAM1ConfigHi]
+ STR r1, [r0, #SDRAM1ConfigHi]
+ STR r1, [r0, #SDRAM1ConfigHi]
+ STR r1, [r0, #SDRAM1ConfigHi]
+ STR r1, [r0, #SDRAM1ConfigHi]
+ STR r1, [r0, #SDRAM1ConfigHi]
+
+# SDRAM mode register: Burst length : 4, sequential
+# CAS latency : 3 cycles
+# Op. mode : standard
+ LDR r1, =0x0032
+ STR r1, [r0, #SDRAM1ConfigLo]
+ MOV r1, #DRAMC_MRS
+ STR r1, [r0, #SDRAM1ConfigHi]
+
+/* Initialize memory system */
+
+/***********************************************************************************
+ Configure Translation Table (Flat mapping : Virtual Address = Physical Address)
+ Base address = 0xA0FFC000 (The Last 16KB of the SDRAM Memory)
+ Size = 16 Kb
+ Descriptors = SDRAM sections are cachable/bufferable (0xA0000000-0xA0FFFFFF)
+ First EMI section is cachable (0x40000000-0x400FFFFF)
+ First SRAM section is cachable/bufferable (0x60000000-0x60003FFF)
+ All the rest non cachable/non bufferable
+***********************************************************************************/
+
+/* IF MMU & CACHE are enabled -> Disable them */
+ MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 */
+ BIC r0, r0, #0x1 /* Clear Bit 0 (MMU) */
+ MCR p15, 0, r0, c1, c0, 0 /* Write back value */
+
+ MOV r0, #0
+ MCR p15, 0, r0, c7, c7, 0 /* invalidate caches */
+ MCR p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+
+ LDR r1, =SGCR1_off_addr /* Clear CACHE Flag on SGCR1 register */
+ LDR r0, [r1]
+ AND r0, r0, #0xFFFFFFDF
+ STR r0, [r1]
+
+# MMU & CACHE Init
+
+ LDR r0, =0xA0FFC000 /* Set start of Translation Table base (16k Boundary) */
+ MCR p15, 0, r0, c2, c0, 0 /* write to CP15 register 2 */
+
+# Create translation Table for flat mapping ( Virtual Address = Physical Address)
+# Top 12 bits of VA is pointer into table
+# Create 4096 entries from 000xxxxx to fffxxxxx
+
+ LDR r1,=0xFFF /* loop counter */
+ MOV r2, #TTBit|Section /* build descriptor pattern in register */
+ ORR r2, r2, #Domain|FullAccess
+
+init_ttb:
+ ORR r3, r2, r1, lsl#20 /* use loop counter to create individual table entries */
+ STR r3,[r0, r1, lsl#2] /* str r3 at TTB base + loopcount*4 */
+ SUBS r1, r1, #1 /* decrement loop counter */
+ BPL init_ttb
+
+# Set cachable attributes for Physical Flash/EMI (3:2)
+
+ LDR r1, =0xA0FFD000
+ LDR r3, [r1]
+ ORR r3, r3, #C
+ STR r3, [r1]
+
+# Set cachable and bufferable attributes for Physical SRAM (3:2)
+
+ LDR r1, =0xA0FFD800
+ LDR r3, [r1]
+ ORR r3, r3, #C|B
+ STR r3, [r1]
+
+# Set cachable and bufferable attributes for Physical SDRAM (3:2)
+ MOV r4, #0
+sdramloop:
+ LDR r1, =0xA0FFE800
+ ADD r1, r1, r4
+ LDR r3, [r1]
+ ORR r3, r3, #C|B
+ STR r3, [r1]
+ ADD r4, r4, #4
+ CMP r4, #0x40
+ BLT sdramloop
+
+# init_domains
+ MOV r0, #(1 << 30) /* must define behaviour for domain 15 (31:30), set client */
+ MCR p15, 0, r0, c3, c0, 0 /* write to CP15 register 5 */
+# set global core configurations
+ MRC p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
+ BIC r0, r0, #(0x1 << 2) /* ensure Cache disabled */
+ ORR r0, r0, #0x1 /* enable MMU */
+ MCR p15, 0, r0, c1, c0, 0 /* write cp15 register 1 */
+
+/******************************************************************************
+EIC initialization
+Description : Initialize the EIC as following :
+ - IRQ disabled
+ - FIQ disabled
+ - IVR contain the load PC opcode (0xF59FF00)
+ - Current priority level equal to 0
+ - All channels are disabled
+ - All channels priority equal to 0
+ - All SIR registers contain offset to the related IRQ table entry
+******************************************************************************/
+
+EIC_INIT:
+ LDR r3, =EIC_Base_addr
+ LDR r4, =0x00000000
+ STR r4, [r3, #ICR_off_addr] /* Disable FIQ and IRQ */
+ STR r4, [r3, #IER_off_addr] /* Disable all channels interrupts */
+ LDR r4, =0xFFFFFFFF
+ STR r4, [r3, #IPR_off_addr] /* Clear all IRQ pending bits */
+ LDR r4, =0x38
+ STR r4, [r3, #FIR_off_addr] /* Disable FIQ channels and clear FIQ pending bits */
+ LDR r4, =0x00000000
+ STR r4, [r3, #CIPR_off_addr] /* Reset the current priority register */
+ LDR r4, =0xE59F0000
+ STR r4, [r3, #IVR_off_addr] /* Write the LDR pc,pc,#offset instruction code in IVR[31:16] */
+ LDR r2, =32 /* 32 Channel to initialize */
+ LDR r0, =EXT03IT_Addr /* Read the address of the IRQs address table */
+ LDR r1, =0x00000FFF
+ AND r0, r0, r1
+ LDR r5, =SIR0_off_addr /* Read SIR0 address */
+ SUB r4, r0, #8 /* subtract 8 for prefetch */
+ LDR r1, =0xF3E8 /* add the offset to the 0x00000000 address(IVR address + 3E8 = 0x00000000) */
+ /* 0xF7E8 used to complete the LDR pc,pc,#offset opcode */
+ ADD r1, r4, r1 /* compute the jump offset */
+EIC_INI:
+ MOV r4, r1, LSL #16 /* Left shift the result */
+ STR r4, [r3, r5] /* Store the result in SIRx register */
+ ADD r1, r1, #4 /* Next IRQ address */
+ ADD r5, r5, #4 /* Next SIR */
+ SUBS r2, r2, #1 /* Decrement the number of SIR registers to initialize */
+ BNE EIC_INI /* If more then continue */
+
+/* Relocate .data section (Copy from ROM to RAM) */
+ LDR r1, =_etext
+ LDR r2, =__data_start
+ LDR r3, =_edata
+LoopRel:
+ CMP r2, r3
+ LDRLO r0, [r1], #4
+ STRLO r0, [r2], #4
+ BLO LoopRel
+
+/* Clear .bss section (Zero init) */
+ MOV r0, #0
+ LDR r1, =__bss_start__
+ LDR r2, =__bss_end__
+LoopZI:
+ CMP r1, r2
+ STRLO r0, [r1], #4
+ BLO LoopZI
+
+/* Call C++ constructors */
+ LDR r0, =__ctors_start__
+ LDR r1, =__ctors_end__
+ctor_loop:
+ CMP r0, r1
+ BEQ ctor_end
+ LDR r2, [r0], #+4
+ STMFD sp!, {r0-r1}
+ MOV lr, pc
+ BX r2
+ LDMFD sp!, {r0-r1}
+ B ctor_loop
+ctor_end:
+
+/* Need to set up standard file handles */
+/* Only used under simulator, normally overide syscall.c */
+# BL initialise_monitor_handles
+
+/* if we use debug version of str7lib this will call the init function */
+
+ BL libdebug
+libdebug:
+
+/* Enter the C code, use B instruction so as to never return */
+/* use BL main if you want to use c++ destructors below */
+ B main
+
+/* Call destructors */
+# LDR r0, =__dtors_start__
+# LDR r1, =__dtors_end__
+dtor_loop:
+# CMP r0, r1
+# BEQ dtor_end
+# LDR r2, [r0], #+4
+# STMFD sp!, {r0-r1}
+# MOV lr, pc
+# BX r2
+# LDMFD sp!, {r0-r1}
+# B dtor_loop
+dtor_end:
+
+/* Return from main, loop forever. */
+exit_loop:
+# B exit_loop
+
+/****************************************************************************
+ Enable & Disable Cache Function definition, these two function may be
+ called by application (main() or any code) whenever user wants to enable
+ or Disable CACHE during program execution.
+****************************************************************************/
+
+ .func Cache_Enable
+
+Cache_Enable:
+ MOV r0, #0 /* dummy */
+ MCR p15, 0, r0, c7, c7, 0 /* invalidate caches */
+ MCR p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ MRC p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
+ ORR r0, r0, #(0x1 << 2) /* enable Cache */
+ MCR p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
+ MOV pc, lr
+
+ .endfunc
+
+ .func Cache_Disable
+
+Cache_Disable:
+ LDR r1, =SGCR1_off_addr /* Clear CACHE Flag on SGCR1 register */
+ LDR r0, [r1]
+ AND r0, r0, #0xFFFFFFDF
+ STR r0, [r1]
+ NOP /* dummy */
+ NOP /* dummy */
+ NOP /* dummy */
+ MOV r0, #0
+ MCR p15, 0, r0, c7, c7, 0 /* invalidate caches */
+ MCR p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ MRC p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
+ BIC r0, r0, #(0x1 << 2) /* ensure Cache disabled */
+ MCR p15, 0, r0, c1, c0, 0 /* write cp15 register 1 */
+ NOP /* dummy */
+ NOP /* dummy */
+ NOP /* dummy */
+ MOV pc, lr
+
+ .endfunc
+
+/* Fosc values, used by libstr7 */
+
+RCCU_Main_Osc: .long FOSC
+
+ .weak libdebug
+
+ .end
Added: trunk/firmware/arm/str/template72x/vector.s
===================================================================
--- trunk/firmware/arm/str/template72x/vector.s (rev 0)
+++ trunk/firmware/arm/str/template72x/vector.s 2008-02-06 13:07:08 UTC (rev 829)
@@ -0,0 +1,598 @@
+/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+ .equ EIC_base_addr, 0xFFFFFC00 /* EIC base address. */
+ .equ CICR_off_addr, 0x04 /* Current Interrupt Channel Register. */
+ .equ IVR_off_addr, 0x18 /* Interrupt Vector Register. */
+ .equ IPR_off_addr, 0x40 /* Interrupt Pending Register. */
+
+ /* set HIRAM 1 for Interrupt Handlers reside in ram Vectors in ram uses 192 bytes
+ Vectors/Handlers uses 1452 bytes, normally 0 */
+
+.ifndef HIRAM
+ .equ HIRAM, 0
+.endif
+
+.ifndef REMAP
+ .equ REMAP, 0
+.endif
+
+ .text
+ .arm
+
+.if REMAP > 1
+ .section .vectram, "ax"
+.else
+ .section .vectrom, "ax"
+.endif
+
+ .global EXT03IT_Addr
+ .global Reset_Vec
+
+/* Note: LDR PC instructions are used here, though branch (B) instructions */
+/* could also be used, unless the ROM is at an address >32MB. */
+
+/*******************************************************************************
+ Exception vectors
+*******************************************************************************/
+
+Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */
+Undef_Vec: LDR pc, Undefined_Addr
+SWI_Vec: LDR pc, SWI_Addr
+PAbt_Vec: LDR pc, Prefetch_Addr
+DAbt_Vec: LDR pc, Abort_Addr
+ NOP /* Reserved vector */
+IRQ_Vec: LDR pc, IRQ_Addr
+FIQ_Vec: LDR pc, FIQ_Addr
+
+/*******************************************************************************
+ Exception handlers address table
+*******************************************************************************/
+
+Reset_Addr: .word _start
+Undefined_Addr: .word UndefinedHandler
+SWI_Addr: .word SWIHandler
+Prefetch_Addr: .word PrefetchHandler
+Abort_Addr: .word AbortHandler
+ .word 0 /* reserved */
+IRQ_Addr: .word IRQHandler
+FIQ_Addr: .word FIQHandler
+
+/*******************************************************************************
+ Peripherals IRQ handlers address table
+*******************************************************************************/
+
+EXT03IT_Addr: .word EXT03ITIRQHandler
+EXT4IT_Addr: .word EXT4ITIRQHandler
+WIUIT_Addr: .word WIUITIRQHandler
+EFT1IT_Addr: .word EFT1ITIRQHandler
+EFT2IT_Addr: .word EFT2ITIRQHandler
+UART1IT_Addr: .word UART1ITIRQHandler
+UART2IT_Addr: .word UART2ITIRQHandler
+DMAIT_Addr: .word DMAITIRQHandler
+DMAS0IT_Addr: .word DMAS0ITIRQHandler
+DMAS1IT_Addr: .word DMAS1ITIRQHandler
+USBHPIT_Addr: .word USBHPITIRQHandler
+USBLPIT_Addr: .word USBLPITIRQHandler
+CANIT_Addr: .word CANITIRQHandler
+BSPI1IT_Addr: .word BSPI1ITIRQHandler
+BSPI2IT_Addr: .word BSPI2ITIRQHandler
+IDEPIT_Addr: .word IDEPITIRQHandler
+RTCIT_Addr: .word RTCITIRQHandler
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ADCIT_Addr: .word ADCITIRQHandler
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+ .word 0 /* reserved */
+EFT2OCA_Addr: .word EFT2OCAIRQHandler
+EFT2OCB_Addr: .word EFT2OCBIRQHandler
+WDGIT_Addr: .word WDGITIRQHandler
+
+/*******************************************************************************
+ Exception Handlers
+*******************************************************************************/
+
+.ifeq HIRAM
+ .section .text, "ax"
+.endif
+
+/*******************************************************************************
+* macro for long jump from ram-rom if handlers are
+* located in ram and are thumb mode
+*******************************************************************************/
+
+.macro mBLX brAddr
+ .ifeq HIRAM
+ BL \brAddr
+ .else
+ LDR r0,=\brAddr
+ MOV lr, pc
+ BX r0
+ .endif
+.endm
+
+/*******************************************************************************
+* Macro Name : SaveContext
+* Description : This macro used to save the context before entering
+ an exception handler.
+* Input : The range of registers to store.
+* Output : none
+*******************************************************************************/
+
+.macro SaveContext reg1 reg2
+ STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */
+ /* address lr_ mode into the stack */
+ MRS r1, spsr /* Save the spsr_mode into r1 */
+ STMFD sp!, {r1} /* Save spsr */
+.endm
+
+/*******************************************************************************
+* Macro Name : RestoreContext
+* Description : This macro used to restore the context to return from
+ an exception handler and continue the program execution.
+* Input : The range of registers to restore.
+* Output : none
+*******************************************************************************/
+
+.macro RestoreContext reg1 reg2
+ LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */
+ MSR spsr_cxsf, r1 /* Restore spsr_mode */
+ LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */
+ /* the exception interrupt */
+.endm
+
+/*******************************************************************************
+* Function Name : IRQHandler
+* Description : This function called when IRQ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+IRQHandler:
+ SUB lr, lr, #4 /* Update the link register */
+ SaveContext r0, r12
+ LDR lr, =ReturnAddress /* Read the return address. */
+ LDR r0, =EIC_base_addr
+ LDR r1, =IVR_off_addr
+ ADD pc, r0, r1 /* Branch to the IRQ handler. */
+ReturnAddress:
+ /* Clear pending bit in EIC (using the proper IPRx) */
+ LDR r0, =EIC_base_addr
+ LDR r2, [r0, #CICR_off_addr]/* Get the IRQ channel number. */
+ MOV r3, #1
+ MOV r3, r3, LSL r2
+ STR r3, [r0, #IPR_off_addr] /* Clear the corresponding IPR bit. */
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : SWIHandler
+* Description : This function called when SWI instruction executed.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+SWIHandler:
+ SaveContext r0, r12 /* r0 holds swi number */
+ MOV r1, sp /* load regs */
+ mBLX SWI_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : UndefinedHandler
+* Description : This function called when undefined instruction
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+UndefinedHandler:
+ SaveContext r0, r12
+ mBLX Undefined_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : PrefetchAbortHandler
+* Description : This function called when Prefetch Abort
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+PrefetchHandler:
+ SUB lr, lr, #4 /* Update the link register. */
+ SaveContext r0, r12
+ mBLX Prefetch_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : DataAbortHandler
+* Description : This function is called when Data Abort
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+AbortHandler:
+ SUB lr, lr, #8 /* Update the link register. */
+ SaveContext r0, r12
+ mBLX Abort_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : FIQHandler
+* Description : This function is called when FIQ
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+FIQHandler:
+ SUB lr, lr, #4 /* Update the link register. */
+ SaveContext r0, r7
+ mBLX FIQ_Handler
+ RestoreContext r0, r7
+
+/*******************************************************************************
+* Macro Name : IRQ_to_SYS
+* Description : This macro used to switch form IRQ mode to SYS mode
+* Input : none.
+* Output : none
+*******************************************************************************/
+
+ .macro IRQ_to_SYS
+ MSR cpsr_c, #0x1F /* Switch to SYS mode */
+ STMFD sp!, {lr} /* Save the link register. */
+ .endm
+
+/*******************************************************************************
+* Macro Name : SYS_to_IRQ
+* Description : This macro used to switch from SYS mode to IRQ mode
+ then to return to IRQHnadler routine.
+* Input : none.
+* Output : none.
+*******************************************************************************/
+
+ .macro SYS_to_IRQ
+ LDMFD sp!, {lr} /* Restore the link register. */
+ MSR cpsr_c, #0xD2 /* Switch to IRQ mode. */
+ MOV pc, lr /* Return to IRQHandler routine to clear the */
+ /* pending bit. */
+ .endm
+
+/*******************************************************************************
+* Function Name : EXT03ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the EXT03ITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ EXT03ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+EXT03ITIRQHandler:
+ IRQ_to_SYS
+ mBLX EXT03IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : EXT4ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the EXT4ITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ EXT4ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+EXT4ITIRQHandler:
+ IRQ_to_SYS
+ mBLX EXT4IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : WIUITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the WIUITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ WIUITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+WIUITIRQHandler:
+ IRQ_to_SYS
+ mBLX WIUIT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : EFT1ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the EFT1ITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ EFT1ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+EFT1ITIRQHandler:
+ IRQ_to_SYS
+ mBLX EFT1IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : EFT2ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the EFT2ITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ EFT2ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+EFT2ITIRQHandler:
+ IRQ_to_SYS
+ mBLX EFT2IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : UART1ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the UART1IRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ UART1ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+UART1ITIRQHandler:
+ IRQ_to_SYS
+ mBLX UART1IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : UART2ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the UART2ITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ UART2ITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+UART2ITIRQHandler:
+ IRQ_to_SYS
+ mBLX UART2IT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : DMAITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ the DMAITIRQHandler function located in 720_it.c.
+ Then to return to IRQ mode after the
+ DMAITIRQHandler function termination.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+DMAITIRQHandler:
+ IRQ_to_SYS
+ mBLX DMAIT_IRQHandler
+ SYS_to_IRQ
+
+/*******************************************************************************
+* Function Name : DMAS0ITIRQHandler
+* Description : This function used to switch to SYS mode before entering
+ ...
[truncated message content] |
