[cadcdev-svn-commits] [SCM] branch master updated. c62573617e4718d48f0ac3fe0cb02d60b78bed32

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- Log -----------------------------------------------------------------
commit c62573617e4718d48f0ac3fe0cb02d60b78bed32
Author: Paul Cercueil <pa...@cr...>
Date:   Thu Jul 10 00:36:06 2025 +0200

    timer: Fine-tune timer rate
    
    The seconds counter has been reported to drift quite significantly vs. a
    wall clock. This is most likely because until now we considered that the
    peripheral clock was a perfect 50.0 MHz, while in practice it is closer
    to 49.9 MHz.
    
    Signed-off-by: Paul Cercueil <pa...@cr...>

-----------------------------------------------------------------------

Summary of changes:
 kernel/arch/dreamcast/kernel/timer.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/kernel/arch/dreamcast/kernel/timer.c b/kernel/arch/dreamcast/kernel/timer.c
index fe5e7853..58a7b067 100644
--- a/kernel/arch/dreamcast/kernel/timer.c
+++ b/kernel/arch/dreamcast/kernel/timer.c
@@ -65,8 +65,11 @@ typedef enum PCK_DIV {
 #define TIMER_TPSC      PCK_DIV_4
 /* Timer IRQ priority levels (0-15) */
 #define TIMER_PRIO      15
-/* Peripheral clock rate (50Mhz) */
-#define TIMER_PCK       50000000
+
+/* Peripheral clock rate (~49.9 Mhz).
+ * The main clock is not exactly 200 MHz, and has been measured at
+ * 199499520 Hz. The peripheral clock is a quarter of that. */
+#define TIMER_PCK       (199499520 / 4)
 
 /* Timer registers, indexed by Timer ID. */
 static const unsigned tcors[] = { TCOR0, TCOR1, TCOR2 };


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