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[cadcdev-svn-commits] [SCM] branch master updated. 48907615f92b09f0df765dd89f27897a6c9ef43e
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From: kosmirror <kos...@us...> - 2025-07-11 22:40:43
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the project "A pseudo Operating System for the Dreamcast.".
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from e4171afbdaf20574a554d8d40f08552e0680db14 (commit)
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- Log -----------------------------------------------------------------
commit 48907615f92b09f0df765dd89f27897a6c9ef43e
Author: Paul Cercueil <pa...@cr...>
Date: Sat May 3 17:45:26 2025 +0200
dmac: Drop old DMAC interface and header
And move the code initializing DMAC on Naomi to the DMAC driver.
Signed-off-by: Paul Cercueil <pa...@cr...>
-----------------------------------------------------------------------
Summary of changes:
kernel/arch/dreamcast/hardware/dmac.c | 33 ++++++++
kernel/arch/dreamcast/include/dc/dmac.h | 140 --------------------------------
kernel/arch/dreamcast/kernel/init.c | 10 +--
3 files changed, 35 insertions(+), 148 deletions(-)
delete mode 100644 kernel/arch/dreamcast/include/dc/dmac.h
diff --git a/kernel/arch/dreamcast/hardware/dmac.c b/kernel/arch/dreamcast/hardware/dmac.c
index d674fbf7..3cde8d4a 100644
--- a/kernel/arch/dreamcast/hardware/dmac.c
+++ b/kernel/arch/dreamcast/hardware/dmac.c
@@ -33,6 +33,20 @@ typedef enum dma_register {
#define REG_CHCR_TRANSFER_END BIT(1)
#define REG_CHCR_DMAC_EN BIT(0)
+#define REG_DMAOR_DDT BIT(15)
+#define REG_DMAOR_PR GENMASK(9, 8)
+#define REG_DMAOR_COD BIT(4)
+#define REG_DMAOR_AE BIT(2)
+#define REG_DMAOR_NMIF BIT(1)
+#define REG_DMAOR_DME BIT(0)
+
+enum dmaor_pr_mode {
+ DMAOR_PR_CH0123,
+ DMAOR_PR_CH0231,
+ DMAOR_PR_CH2013,
+ DMAOR_PR_ROUND_ROBIN,
+};
+
static const dma_config_t *channels_cfg[4];
static const irq_t channel_to_irq[] = {
@@ -173,3 +187,22 @@ void dma_transfer_abort(dma_channel_t channel) {
dmac_write(channel, DMA_REG_CHCR, 0);
genwait_wake_all((void *)&channels_cfg[channel]);
}
+
+void dma_init(void) {
+ /* Set default settings for DMA #2.
+ * These are set by the bios on Dreamcast, but should be set by the OS
+ * on Naomi. */
+ uint32_t chcr, dmaor;
+
+ dmac_write(2, DMA_REG_SAR, 0);
+
+ chcr = FIELD_PREP(REG_CHCR_SRC_ADDRMODE, DMA_ADDRMODE_INCREMENT)
+ | FIELD_PREP(REG_CHCR_REQUEST, DMA_REQUEST_EXTERNAL_MEM_TO_DEV)
+ | FIELD_PREP(REG_CHCR_DMAC_EN, 1);
+ dmac_write(2, DMA_REG_CHCR, chcr);
+
+ dmaor = REG_DMAOR_DDT
+ | FIELD_PREP(REG_DMAOR_PR, DMAOR_PR_CH2013)
+ | REG_DMAOR_DME;
+ dmac_write(0, DMA_REG_DMAOR, dmaor);
+}
diff --git a/kernel/arch/dreamcast/include/dc/dmac.h b/kernel/arch/dreamcast/include/dc/dmac.h
deleted file mode 100644
index 949e42e7..00000000
--- a/kernel/arch/dreamcast/include/dc/dmac.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* KallistiOS ##version##
-
- dmac.h
- Copyright (C) 2023 Andy Barajas
-
-*/
-
-/** \file dc/dmac.h
- \brief Macros to access the DMA controller registers.
- \ingroup system_dmac
-
- This header provides a set of macros to facilitate checking
- the values of various DMA channels on the system.
-
- DMA channel 0 and its registers (DMAC_SAR0, DMAC_DAR0, DMAC_DMATCR0,
- DMAC_CHCR0) are used by the hardware and not accessible to us but are
- documented here anyway.
-
- DMA channel 2 is strictly used to transfer data to the PVR/TA.
-
- DMA channel 1 & 3 are free to use.
-
- \author Andy Barajas
-*/
-
-#ifndef __DC_DMAC_H
-#define __DC_DMAC_H
-
-#include <sys/cdefs.h>
-__BEGIN_DECLS
-
-/** \defgroup system_dmac DMA
- \brief Driver for the SH4's Direct Memory Access
- Controller
- \ingroup system
-
- @{
-*/
-
-#define DMAC_BASE 0xffa00000
-
-/** \name DMA Source Address Registers (SAR0-SAR3)
-
- These registers designate the source address for DMA transfers.
- Currently we only support 32-byte boundary addresses.
-
- @{
- */
-
-#define DMAC_SAR0 (*((vuint32 *)(DMAC_BASE + 0x00)))
-#define DMAC_SAR1 (*((vuint32 *)(DMAC_BASE + 0x10)))
-#define DMAC_SAR2 (*((vuint32 *)(DMAC_BASE + 0x20)))
-#define DMAC_SAR3 (*((vuint32 *)(DMAC_BASE + 0x30)))
-
-/** @} */
-
-/** \name DMA Destination Address Registers (DAR0-DAR3)
-
- These registers designate the destination address for DMA transfers.
- Currently we only support 32-byte boundary addresses.
-
- @{
- */
-
-#define DMAC_DAR0 (*((vuint32 *)(DMAC_BASE + 0x04)))
-#define DMAC_DAR1 (*((vuint32 *)(DMAC_BASE + 0x14)))
-#define DMAC_DAR2 (*((vuint32 *)(DMAC_BASE + 0x24)))
-#define DMAC_DAR3 (*((vuint32 *)(DMAC_BASE + 0x34)))
-
-/** @} */
-
-/** \name DMA Transfer Count Registers (DMATCR0-DMATCR3)
-
- These registers define the transfer count for each DMA channel. The count
- is defined as: num_bytes_to_transfer/32
-
- @{
- */
-
-#define DMAC_DMATCR0 (*((vuint32 *)(DMAC_BASE + 0x08)))
-#define DMAC_DMATCR1 (*((vuint32 *)(DMAC_BASE + 0x18)))
-#define DMAC_DMATCR2 (*((vuint32 *)(DMAC_BASE + 0x28)))
-#define DMAC_DMATCR3 (*((vuint32 *)(DMAC_BASE + 0x38)))
-
-/** @} */
-
-/** \name DMA Channel Control Registers (CHCR0-CHCR3)
-
- These registers configure the operating mode and transfer methodology for
- each channel.
-
- For DMAC_CHCR2, it should always be set to 0x12c1 (source address
- incremented, burst mode, interrupt disable, DMA enable).
-
- For DMAC_CHCR1 and DMAC_CHCR3, it would probably be set to 0x1241
- (source address incremented, cycle steal mode, interrupt disable,
- DMA enable).
-
- @{
- */
-
-#define DMAC_CHCR0 (*((vuint32 *)(DMAC_BASE + 0x0c)))
-#define DMAC_CHCR1 (*((vuint32 *)(DMAC_BASE + 0x1c)))
-#define DMAC_CHCR2 (*((vuint32 *)(DMAC_BASE + 0x2c)))
-#define DMAC_CHCR3 (*((vuint32 *)(DMAC_BASE + 0x3c)))
-
-/** @} */
-
-
-/**
- \brief A register that dictates the overall operation of the DMAC.
-
- So far we only use it check the status of DMA operations.
-
- */
-#define DMAC_DMAOR (*((vuint32 *)(DMAC_BASE + 0x40)))
-
-/** \name List of helpful masks to check operations
-
- The DMAOR_STATUS_MASK captures the On-Demand Data Transfer Mode (Bit 15),
- Address Error Flag (Bit 2), NMI Flag (Bit 1), and DMAC Master Enable (Bit 0).
-
- The DMAOR_NORMAL_OPERATION is a state where DMAC Master Enable is active,
- and the On-Demand Data Transfer Mode is not set, with no address errors
- or NMI inputs.
-
- @{
-*/
-
-#define DMAOR_STATUS_MASK 0x8007
-#define DMAOR_NORMAL_OPERATION 0x8001
-
-/** @} */
-
-/** @} */
-
-__END_DECLS
-
-#endif /* __DC_DMAC_H */
-
diff --git a/kernel/arch/dreamcast/kernel/init.c b/kernel/arch/dreamcast/kernel/init.c
index 765f8850..7f75feb7 100644
--- a/kernel/arch/dreamcast/kernel/init.c
+++ b/kernel/arch/dreamcast/kernel/init.c
@@ -25,7 +25,6 @@
#include <dc/pvr.h>
#include <dc/vmufs.h>
#include <dc/syscalls.h>
-#include <dc/dmac.h>
#include "initall_hdrs.h"
@@ -40,6 +39,7 @@ extern uintptr_t _bss_start, end;
extern void _init(void);
extern void _fini(void);
extern void __verify_newlib_patch();
+extern void dma_init(void);
void (*__kos_init_early_fn)(void) __attribute__((weak,section(".data"))) = NULL;
@@ -280,13 +280,7 @@ void arch_main(void) {
uint8 *bss_start = (uint8 *)(&_bss_start);
int rv;
- if (KOS_PLATFORM_IS_NAOMI) {
- /* Ugh. I'm really not sure why we have to set up these DMA registers this
- way on boot, but failing to do so breaks maple... */
- DMAC_SAR2 = 0;
- DMAC_CHCR2 = 0x1201;
- DMAC_DMAOR = 0x8201;
- }
+ dma_init();
/* Ensure the WDT is not enabled from a previous session */
wdt_disable();
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A pseudo Operating System for the Dreamcast.
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