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[cadcdev-svn-commits] [SCM] branch master updated. v2.0.0-1191-g70337bb
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From: ljsebald <ljs...@us...> - 2023-12-01 20:17:37
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "A pseudo Operating System for the Dreamcast.".
The branch, master has been updated
via 70337bb739622aa55556972848cd84af3e7de28a (commit)
via 364b9c880c4b65627de9b5cba7b2cf12ca9e3e6d (commit)
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- Log -----------------------------------------------------------------
commit 70337bb739622aa55556972848cd84af3e7de28a
Merge: 25be1fb 364b9c8
Author: Lawrence Sebald <ljs...@us...>
Date: Fri Dec 1 15:14:27 2023 -0500
Merge pull request #374 from Dreamcast-Projects/thdswitch_speed
* Use pair single precision data transfer
* Removed unused global
* Fixed bug in thdswitch. Added commented out sections
* Fixed spacing and address feedback
* Removed extra add
* Fix spacing
* Fix copyright
commit 364b9c880c4b65627de9b5cba7b2cf12ca9e3e6d
Author: Andress Barajas <and...@gm...>
Date: Thu Nov 30 23:54:37 2023 -0800
Fix copyright
commit ab08bdd386250c3a7f53705bd8b27a8cb9ebc0e7
Author: Andress Barajas <and...@gm...>
Date: Thu Nov 30 23:53:52 2023 -0800
Fix spacing
commit 760c20121cdfcb7dcded3d6012323792b12fba85
Author: Andress Barajas <and...@gm...>
Date: Thu Nov 30 23:51:03 2023 -0800
Removed extra add
commit 5a04eaf7a9260ba8a955ddf8b4116aa5281e73e5
Author: Andress Barajas <and...@gm...>
Date: Thu Nov 30 23:48:56 2023 -0800
Fixed spacing and address feedback
commit b430a7017c3b05197363dfaa11b1ed1ee9fd5cf2
Merge: 43b9712 6ffd6a1
Author: Andy Barajas <and...@gm...>
Date: Sun Nov 26 15:08:47 2023 -0800
Merge branch 'KallistiOS:master' into thdswitch_speed
commit 43b9712f7c067466a003d2353c5188569271c1f3
Merge: d9aaa49 8b11983
Author: Andy Barajas <and...@gm...>
Date: Sun Nov 26 09:04:28 2023 -0800
Merge branch 'KallistiOS:master' into thdswitch_speed
commit d9aaa493630a61f80d6f7041806c0b7b1874a1f0
Author: Andress Barajas <and...@gm...>
Date: Wed Nov 22 14:13:51 2023 -0800
Fixed bug in thdswitch. Added commented out sections
commit 0dad23dad59142ca4bf90e96f207171bdee2957d
Author: Andress Barajas <and...@gm...>
Date: Wed Nov 22 10:10:07 2023 -0800
Removed unused global
commit ad4cedb0960b625f16002b1217b1f2aabb91da51
Author: Andress Barajas <and...@gm...>
Date: Wed Nov 22 10:01:13 2023 -0800
Use pair single precision data transfer
-----------------------------------------------------------------------
Summary of changes:
include/kos/thread.h | 2 -
kernel/arch/dreamcast/include/arch/irq.h | 34 +-
kernel/arch/dreamcast/kernel/entry.s | 581 +++++++++++++++----------------
kernel/arch/dreamcast/kernel/irq.c | 18 +-
kernel/arch/dreamcast/kernel/thdswitch.s | 169 +++++----
5 files changed, 383 insertions(+), 421 deletions(-)
diff --git a/include/kos/thread.h b/include/kos/thread.h
index c00b4ab..cf353e2 100644
--- a/include/kos/thread.h
+++ b/include/kos/thread.h
@@ -19,8 +19,6 @@ __BEGIN_DECLS
#include <sys/reent.h>
#include <stdint.h>
-#include <stdint.h>
-
/** \file kos/thread.h
\brief Threading support.
\ingroup kthreads
diff --git a/kernel/arch/dreamcast/include/arch/irq.h b/kernel/arch/dreamcast/include/arch/irq.h
index de70c60..2f782ee 100644
--- a/kernel/arch/dreamcast/include/arch/irq.h
+++ b/kernel/arch/dreamcast/include/arch/irq.h
@@ -20,6 +20,7 @@
#ifndef __ARCH_IRQ_H
#define __ARCH_IRQ_H
+#include <stdint.h>
#include <sys/cdefs.h>
__BEGIN_DECLS
@@ -44,19 +45,20 @@ __BEGIN_DECLS
\headerfile arch/irq.h
*/
typedef struct irq_context {
- uint32 r[16]; /**< \brief 16 general purpose (integer) registers */
- uint32 pc; /**< \brief Program counter */
- uint32 pr; /**< \brief Procedure register (aka return address) */
- uint32 gbr; /**< \brief Global base register */
- uint32 vbr; /**< \brief Vector base register */
- uint32 mach; /**< \brief Multiply-and-accumulate register (high) */
- uint32 macl; /**< \brief Multiply-and-accumulate register (low) */
- uint32 sr; /**< \brief Status register */
- uint32 frbank[16]; /**< \brief Secondary floating poing registers */
- uint32 fr[16]; /**< \brief Primary floating point registers */
- uint32 fpscr; /**< \brief Floating-point status/control register */
- uint32 fpul; /**< \brief Floatint-point communication register */
-} irq_context_t;
+ uint32_t r[16]; /**< \brief 16 general purpose (integer) registers */
+ uint32_t pc; /**< \brief Program counter */
+ uint32_t pr; /**< \brief Procedure register (aka return address) */
+ uint32_t gbr; /**< \brief Global base register */
+ uint32_t vbr; /**< \brief Vector base register */
+ uint32_t mach; /**< \brief Multiply-and-accumulate register (high) */
+ uint32_t macl; /**< \brief Multiply-and-accumulate register (low) */
+ uint32_t sr; /**< \brief Status register */
+ uint32_t fpul; /**< \brief Floating-point communication register */
+ uint32_t frbank[16]; /**< \brief Secondary floating poing registers */
+ uint32_t fr[16]; /**< \brief Primary floating point registers */
+ uint32_t fpscr; /**< \brief Floating-point status/control register */
+ uint8_t padding[28]; /**< \brief Padding to make the struct size 256 bytes */
+} irq_context_t __attribute((aligned(32)));
/* A couple of architecture independent access macros */
/** \brief Fetch the program counter from an irq_context_t.
@@ -232,7 +234,7 @@ typedef struct irq_context {
#define TIMER_IRQ EXC_TMU0_TUNI0
/** \brief The type of an interrupt identifier */
-typedef uint32 irq_t;
+typedef uint32_t irq_t;
/** \brief The type of an IRQ handler
\param source The IRQ that caused the handler to be called.
@@ -330,8 +332,8 @@ irq_context_t *irq_get_context(void);
to the architecture maximum.
\param usermode 1 to run the routine in user mode, 0 for supervisor.
*/
-void irq_create_context(irq_context_t *context, uint32 stack_pointer,
- uint32 routine, uint32 *args, int usermode);
+void irq_create_context(irq_context_t *context, uint32_t stack_pointer,
+ uint32_t routine, uint32_t *args, int usermode);
/* Enable/Disable interrupts */
/** \brief Disable interrupts.
diff --git a/kernel/arch/dreamcast/kernel/entry.s b/kernel/arch/dreamcast/kernel/entry.s
index 5624fb6..ddf330b 100644
--- a/kernel/arch/dreamcast/kernel/entry.s
+++ b/kernel/arch/dreamcast/kernel/entry.s
@@ -1,7 +1,8 @@
! KallistiOS ##version##
!
! arch/dreamcast/kernel/entry.s
-! (c)2000-2001 Megan Potter
+! Copyright (C) 2003 Megan Potter
+! Copyright (C) 2023 Colton Pawielski
!
! Assembler code for entry and exit to/from the kernel via exceptions
!
@@ -14,12 +15,12 @@
! for a context switcher (or especially a timer! =) but it can
! be optimized later.
- .text
- .align 2
- .globl _irq_srt_addr
- .globl _irq_handle_exception
- .globl _irq_save_regs
- .globl _irq_force_return
+ .text
+ .align 2
+ .globl _irq_srt_addr
+ .globl _irq_handle_exception
+ .globl _irq_save_regs
+ .globl _irq_force_return
! Static kernel-mode stack; we can get away with this because in our
! tiny microkernel, only one thread will ever actually be sitting inside
@@ -29,200 +30,170 @@
! mis-mapped user-mode stack pointers, etc. It also opens the door for
! hard real-time interrupts and exceptions that interrupt the kernel
! itself.
- .space 4096 ! One page
+ .space 4096 ! One page
krn_stack:
! All exception vectors lead to Rome (i.e., this label).
+ .align 2
_irq_save_regs:
! On the SH4, an exception triggers a toggle of RB in SR. So all
! the R0-R7 registers were convienently saved for us.
- mov.l _irq_srt_addr,r0 ! Grab the location of the reg store
- add #0x20,r0 ! Start at the top of the BANK regs
- stc.l r7_bank,@-r0 ! Save R7
- stc.l r6_bank,@-r0 ! Save R6
- stc.l r5_bank,@-r0 ! Save R5
- stc.l r4_bank,@-r0 ! Save R4
- stc.l r3_bank,@-r0 ! Save R3
- stc.l r2_bank,@-r0 ! Save R2
- stc.l r1_bank,@-r0 ! Save R1
- stc.l r0_bank,@-r0 ! Save R0
-
- mov.l r8,@(0x20,r0) ! save R8
- mov.l r9,@(0x24,r0) ! save R9
- mov.l r10,@(0x28,r0) ! save R10
- mov.l r11,@(0x2c,r0) ! save R11
- mov.l r12,@(0x30,r0) ! save R12
- mov.l r13,@(0x34,r0) ! save R13
- mov.l r14,@(0x38,r0) ! save R14
- mov.l r15,@(0x3c,r0) ! save R15 (SP)
- add #0x5c,r0 ! readjust register pointer
- stc.l ssr,@-r0 ! save SSR 0x58
- sts.l macl,@-r0 ! save MACL 0x54
- sts.l mach,@-r0 ! save MACH 0x50
- stc.l vbr,@-r0 ! save VBR 0x4c
- stc.l gbr,@-r0 ! save GBR 0x48
- sts.l pr,@-r0 ! save PR 0x44
- stc.l spc,@-r0 ! save PC 0x40
-
- add #0x60,r0 ! readjust register pointer
- add #0x44,r0
- sts.l fpul,@-r0 ! save FPUL 0xe0
- sts.l fpscr,@-r0 ! save FPSCR 0xdc
- mov #0,r2 ! Set known FP flags
- lds r2,fpscr
- fmov.s fr15,@-r0 ! save FR15 0xd8
- fmov.s fr14,@-r0 ! save FR14
- fmov.s fr13,@-r0 ! save FR13
- fmov.s fr12,@-r0 ! save FR12
- fmov.s fr11,@-r0 ! save FR11
- fmov.s fr10,@-r0 ! save FR10
- fmov.s fr9,@-r0 ! save FR9
- fmov.s fr8,@-r0 ! save FR8
- fmov.s fr7,@-r0 ! save FR7
- fmov.s fr6,@-r0 ! save FR6
- fmov.s fr5,@-r0 ! save FR5
- fmov.s fr4,@-r0 ! save FR4
- fmov.s fr3,@-r0 ! save FR3
- fmov.s fr2,@-r0 ! save FR2
- fmov.s fr1,@-r0 ! save FR1
- fmov.s fr0,@-r0 ! save FR0 0x9c
- frchg ! Second FP bank
- fmov.s fr15,@-r0 ! save FR15 0x98
- fmov.s fr14,@-r0 ! save FR14
- fmov.s fr13,@-r0 ! save FR13
- fmov.s fr12,@-r0 ! save FR12
- fmov.s fr11,@-r0 ! save FR11
- fmov.s fr10,@-r0 ! save FR10
- fmov.s fr9,@-r0 ! save FR9
- fmov.s fr8,@-r0 ! save FR8
- fmov.s fr7,@-r0 ! save FR7
- fmov.s fr6,@-r0 ! save FR6
- fmov.s fr5,@-r0 ! save FR5
- fmov.s fr4,@-r0 ! save FR4
- fmov.s fr3,@-r0 ! save FR3
- fmov.s fr2,@-r0 ! save FR2
- fmov.s fr1,@-r0 ! save FR1
- fmov.s fr0,@-r0 ! save FR0 0x5c
- frchg ! First FP bank again
-
- ! Setup our kernel-mode stack
- mov.l stkaddr,r15
-
- ! Before we enter the main C code again, re-enable exceptions
- ! (but not interrupts) so we can still debug inside handlers.
- bsr _irq_disable
- nop
-
- ! R4 still contains the exception code
- mov.l hdl_except,r2 ! Call handle_exception
- jsr @r2
- nop
- bra _save_regs_finish
- nop
+ mov.l _irq_srt_addr, r0 ! Grab the location of the reg store
+ add #0x20, r0 ! Start at the top of the BANK regs
+ stc.l r7_bank, @-r0 ! Save R7
+ stc.l r6_bank, @-r0 ! Save R6
+ stc.l r5_bank, @-r0 ! Save R5
+ stc.l r4_bank, @-r0 ! Save R4
+ stc.l r3_bank, @-r0 ! Save R3
+ stc.l r2_bank, @-r0 ! Save R2
+ stc.l r1_bank, @-r0 ! Save R1
+ stc.l r0_bank, @-r0 ! Save R0
+
+ mov.l r8,@(0x20,r0) ! save R8
+ mov.l r9,@(0x24,r0) ! save R9
+ mov.l r10,@(0x28,r0) ! save R10
+ mov.l r11,@(0x2c,r0) ! save R11
+ mov.l r12,@(0x30,r0) ! save R12
+ mov.l r13,@(0x34,r0) ! save R13
+ mov.l r14,@(0x38,r0) ! save R14
+ mov.l r15,@(0x3c,r0) ! save R15 (SP)
+ add #0x5c, r0 ! readjust register pointer
+ stc.l ssr, @-r0 ! save SSR 0x58
+ sts.l macl, @-r0 ! save MACL 0x54
+ sts.l mach, @-r0 ! save MACH 0x50
+ stc.l vbr, @-r0 ! save VBR 0x4c
+ stc.l gbr, @-r0 ! save GBR 0x48
+ sts.l pr, @-r0 ! save PR 0x44
+ stc.l spc, @-r0 ! save PC 0x40
+
+ add #0xA4, r0 ! readjust register pointer
+ sts.l fpscr, @-r0 ! save FPSCR 0xdc
+ mov #0, r2 ! Set known FP flags
+ lds r2, fpscr
+ fschg ! Switch to pair FP moves
+ fmov.d dr14, @-r0 ! save FR14 & FR15
+ fmov.d dr12, @-r0 ! save FR12 & FR13
+ fmov.d dr10, @-r0 ! save FR10 & FR11
+ fmov.d dr8, @-r0 ! save FR8 & FR9
+ fmov.d dr6, @-r0 ! save FR6 & FR7
+ fmov.d dr4, @-r0 ! save FR4 & FR5
+ fmov.d dr2, @-r0 ! save FR2 & FR3
+ fmov.d dr0, @-r0 ! save FR0 & FR1
+ frchg ! Second FP bank
+ fmov.d dr14, @-r0 ! save FR14 & FR15
+ fmov.d dr12, @-r0 ! save FR12 & FR13
+ fmov.d dr10, @-r0 ! save FR10 & FR11
+ fmov.d dr8, @-r0 ! save FR8 & FR9
+ fmov.d dr6, @-r0 ! save FR6 & FR7
+ fmov.d dr4, @-r0 ! save FR4 & FR5
+ fmov.d dr2, @-r0 ! save FR2 & FR3
+ fmov.d dr0, @-r0 ! save FR0 & FR1
+ fschg ! Switch to single FP moves
+ frchg ! First FP bank again
+ sts.l fpul, @-r0 ! save FPUL
+
+ ! Setup our kernel-mode stack
+ mov.l stkaddr, r15
+
+ ! Before we enter the main C code again, re-enable exceptions
+ ! (but not interrupts) so we can still debug inside handlers.
+ bsr _irq_disable
+ nop
+
+ ! R4 still contains the exception code
+ mov.l hdl_except, r2 ! Call handle_exception
+ jsr @r2
+ nop
+ bra _save_regs_finish
+ nop
! irq_force_return() jumps here; make sure we're in register
! bank 1 (as opposed to 0)
+ .align 2
_irq_force_return:
- mov.l _irqfr_or,r1
- stc sr,r0
- or r1,r0
- ldc r0,sr
- bra _save_regs_finish
- nop
-
- .align 2
+ mov.l _irqfr_or, r1
+ stc sr, r0
+ or r1, r0
+ ldc r0, sr
+ bra _save_regs_finish
+ nop
+
+ .align 2
_irqfr_or:
- .long 0x20000000
+ .long 0x20000000
stkaddr:
- .long krn_stack
+ .long krn_stack
! Now restore all the registers and jump back to the thread
+ .align 2
_save_regs_finish:
- mov.l _irq_srt_addr, r1 ! Get register store address
- ldc.l @r1+,r0_bank ! restore R0 (r1 is now _irq_srt_addr+0)
- ldc.l @r1+,r1_bank ! restore R1
- ldc.l @r1+,r2_bank ! restore R2
- ldc.l @r1+,r3_bank ! restore R3
- ldc.l @r1+,r4_bank ! restore R4
- ldc.l @r1+,r5_bank ! restore R5
- ldc.l @r1+,r6_bank ! restore R6
- ldc.l @r1+,r7_bank ! restore R7
- add #-32,r1 ! Go back to the front
- mov.l @(0x20,r1), r8 ! restore R8 (r1 is now ...+0)
- mov.l @(0x24,r1), r9 ! restore R9
- mov.l @(0x28,r1), r10 ! restore R10
- mov.l @(0x2c,r1), r11 ! restore R11
- mov.l @(0x30,r1), r12 ! restore R12
- mov.l @(0x34,r1), r13 ! restore R13
- mov.l @(0x38,r1), r14 ! restore R14
- mov.l @(0x3c,r1), r15 ! restore program's stack
-
- add #0x40,r1 ! jump up to status words
- ldc.l @r1+,spc ! restore SPC 0x40 (r1 is now +0x40)
- lds.l @r1+,pr ! restore PR 0x44 (+0x44)
- ldc.l @r1+,gbr ! restore GBR 0x48 (+0x48)
-! ldc.l @r1+,vbr ! restore VBR (don't play with VBR)
- add #4,r1 ! (+0x4c)
- lds.l @r1+,mach ! restore MACH 0x50 (+0x50)
- lds.l @r1+,macl ! restore MACL 0x54 (+0x54)
- ldc.l @r1+,ssr ! restore SSR 0x58 (+0x58)
-
- mov #0,r2 ! Set known FP flags (+0x5c)
- lds r2,fpscr
- frchg ! Second FP bank
- fmov.s @r1+,fr0 ! restore FR0 0x5c
- fmov.s @r1+,fr1 ! restore FR1
- fmov.s @r1+,fr2 ! restore FR2
- fmov.s @r1+,fr3 ! restore FR3
- fmov.s @r1+,fr4 ! restore FR4
- fmov.s @r1+,fr5 ! restore FR5
- fmov.s @r1+,fr6 ! restore FR6
- fmov.s @r1+,fr7 ! restore FR7
- fmov.s @r1+,fr8 ! restore FR8
- fmov.s @r1+,fr9 ! restore FR9
- fmov.s @r1+,fr10 ! restore FR10
- fmov.s @r1+,fr11 ! restore FR11
- fmov.s @r1+,fr12 ! restore FR12
- fmov.s @r1+,fr13 ! restore FR13
- fmov.s @r1+,fr14 ! restore FR14
- fmov.s @r1+,fr15 ! restore FR15 0x98
- frchg ! First FP bank
- fmov.s @r1+,fr0 ! restore FR0 0x9c
- fmov.s @r1+,fr1 ! restore FR1
- fmov.s @r1+,fr2 ! restore FR2
- fmov.s @r1+,fr3 ! restore FR3
- fmov.s @r1+,fr4 ! restore FR4
- fmov.s @r1+,fr5 ! restore FR5
- fmov.s @r1+,fr6 ! restore FR6
- fmov.s @r1+,fr7 ! restore FR7
- fmov.s @r1+,fr8 ! restore FR8
- fmov.s @r1+,fr9 ! restore FR9
- fmov.s @r1+,fr10 ! restore FR10
- fmov.s @r1+,fr11 ! restore FR11
- fmov.s @r1+,fr12 ! restore FR12
- fmov.s @r1+,fr13 ! restore FR13
- fmov.s @r1+,fr14 ! restore FR14
- fmov.s @r1+,fr15 ! restore FR15 0xd8
- lds.l @r1+,fpscr ! restore FPSCR 0xdc
- lds.l @r1+,fpul ! restore FPUL 0xe0
-
-! add #-0x70,r1 ! jump back to registers
-! add #-0x34,r1
-! mov.l @(0,r1),r0 ! restore R0
-! mov.l @(4,r1),r1 ! restore R1
- mov #2,r0
-
- rte ! return
- nop
-
- .align 2
+ mov.l _irq_srt_addr, r1 ! Get register store address
+ ldc.l @r1+, r0_bank ! restore R0 (r1 is now _irq_srt_addr+0)
+ ldc.l @r1+, r1_bank ! restore R1
+ ldc.l @r1+, r2_bank ! restore R2
+ ldc.l @r1+, r3_bank ! restore R3
+ ldc.l @r1+, r4_bank ! restore R4
+ ldc.l @r1+, r5_bank ! restore R5
+ ldc.l @r1+, r6_bank ! restore R6
+ ldc.l @r1+, r7_bank ! restore R7
+ add #-32, r1 ! Go back to the front
+ mov.l @(0x20,r1), r8 ! restore R8 (r1 is now ...+0)
+ mov.l @(0x24,r1), r9 ! restore R9
+ mov.l @(0x28,r1), r10 ! restore R10
+ mov.l @(0x2c,r1), r11 ! restore R11
+ mov.l @(0x30,r1), r12 ! restore R12
+ mov.l @(0x34,r1), r13 ! restore R13
+ mov.l @(0x38,r1), r14 ! restore R14
+ mov.l @(0x3c,r1), r15 ! restore program's stack
+
+ add #0x40, r1 ! jump up to status words
+ ldc.l @r1+, spc ! restore SPC 0x40 (r1 is now +0x40)
+ lds.l @r1+, pr ! restore PR 0x44 (+0x44)
+ ldc.l @r1+, gbr ! restore GBR 0x48 (+0x48)
+! ldc.l @r1+, vbr ! restore VBR (don't play with VBR)
+ add #4, r1 ! (+0x4c)
+ lds.l @r1+, mach ! restore MACH 0x50 (+0x50)
+ lds.l @r1+, macl ! restore MACL 0x54 (+0x54)
+ ldc.l @r1+, ssr ! restore SSR 0x58 (+0x58)
+
+ lds.l @r1+, fpul ! restore FPUL
+ mov #0, r2 ! Set known FP flags (+0x5c)
+ lds r2, fpscr
+ frchg ! Second FP bank
+ fschg ! Switch to pair FP moves
+ fmov.d @r1+, dr0 ! restore FR0 & FR1
+ fmov.d @r1+, dr2 ! restore FR2 & FR3
+ fmov.d @r1+, dr4 ! restore FR4 & FR5
+ fmov.d @r1+, dr6 ! restore FR6 & FR7
+ fmov.d @r1+, dr8 ! restore FR8 & FR9
+ fmov.d @r1+, dr10 ! restore FR10 & FR11
+ fmov.d @r1+, dr12 ! restore FR12 & FR13
+ fmov.d @r1+, dr14 ! restore FR14 & FR15
+ frchg ! First FP bank
+ fmov.d @r1+, dr0 ! restore FR0 & FR1
+ fmov.d @r1+, dr2 ! restore FR2 & FR3
+ fmov.d @r1+, dr4 ! restore FR4 & FR5
+ fmov.d @r1+, dr6 ! restore FR6 & FR7
+ fmov.d @r1+, dr8 ! restore FR8 & FR9
+ fmov.d @r1+, dr8 ! restore FR8 & FR9
+ fmov.d @r1+, dr10 ! restore FR10 & FR11
+ fmov.d @r1+, dr12 ! restore FR12 & FR13
+ fmov.d @r1+, dr14 ! restore FR14 & FR15
+ lds.l @r1+, fpscr ! restore FPSCR 0xdc
+
+ mov #2, r0
+
+ rte ! return
+ nop
+
+ .align 2
_irq_srt_addr:
- .long 0 ! Save Regs Table -- this is an indirection
- ! so we can easily swap out pointers during a
- ! context switch.
+ .long 0 ! Save Regs Table -- this is an indirection
+ ! so we can easily swap out pointers during a
+ ! context switch.
hdl_except:
- .long _irq_handle_exception
+ .long _irq_handle_exception
! Special case handler for TLB miss exceptions. There are two reasons
@@ -238,80 +209,80 @@ hdl_except:
! !!NOTE!! This is highly dependent on the structure of the MMU tables
! in mmu.h and the MMU code in mmu.c. If either of those change, this will
! likely need to change as well.
- .text
- .align 2
+ .text
+ .align 2
tlb_miss_hnd:
- ! Get the exception event code; we want to handle only
- ! 0x0040 (ITLB_MISS/DTLB_MISS_READ) or 0x0060 (DTLB_MISS_WRITE)
- mov #-1,r3 ! 0xff000024 (EXPEVT) -> r3
- shll16 r3
- shll8 r3
- add #0x24,r3
- mov.l @r3,r0 ! Get EXPEVT
+ ! Get the exception event code; we want to handle only
+ ! 0x0040 (ITLB_MISS/DTLB_MISS_READ) or 0x0060 (DTLB_MISS_WRITE)
+ mov #-1, r3 ! 0xff000024 (EXPEVT) -> r3
+ shll16 r3
+ shll8 r3
+ add #0x24, r3
+ mov.l @r3, r0 ! Get EXPEVT
- mov #0x40,r1 ! 0x0040 -> r1
+ mov #0x40, r1 ! 0x0040 -> r1
- cmp/eq r0,r1
- bt.s tmh_doit
- mov #0x60,r1
+ cmp/eq r0, r1
+ bt.s tmh_doit
+ mov #0x60, r1
- cmp/eq r0,r1
- bt tmh_doit
+ cmp/eq r0, r1
+ bt tmh_doit
- ! It's not one of the MISS codes, just send it on to the normal
- ! irq processing.
- bra _irq_save_regs
- mov #2,r4
+ ! It's not one of the MISS codes, just send it on to the normal
+ ! irq processing.
+ bra _irq_save_regs
...<truncated>...
hooks/post-receive
--
A pseudo Operating System for the Dreamcast.
|
