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[cadcdev-svn-commits] [SCM] branch master updated. v2.0.0-1002-g90e09d8
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From: darcagn <da...@us...> - 2023-08-03 20:35:17
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- Log -----------------------------------------------------------------
commit 90e09d81d7c1f9dc3f31290a8fff94e4d5ff304a
Merge: f5d4472 d95d266
Author: Lawrence Sebald <ljs...@us...>
Date: Thu Aug 3 16:08:31 2023 -0400
Merge pull request #246 from KallistiOS/non-magical_map
Defines for memory areas
commit f5d4472052a62ae1b6f4a3a7c280426a8c49f4a4
Merge: cddc955 6bac3d5
Author: Lawrence Sebald <ljs...@us...>
Date: Thu Aug 3 16:06:44 2023 -0400
Merge pull request #257 from KallistiOS/newstable
Stabilize 13.2; update binutils to 2.41; revise documentation, configs, and Dockerfile
commit 6bac3d533e86fc05a6ecd6356d3e8af95d498f6b
Author: darc <da...@pr...>
Date: Sun Jul 30 22:08:19 2023 -0500
Stabilize 13.2; update binutils to 2.41; revise documentation, configs, and Dockerfile
commit d95d2668c8c520cb5782a136c2c4615eb332a985
Author: Donald Haase <qu...@co...>
Date: Sun Jul 9 14:01:48 2023 -0400
Final cleanup
commit d521b5d751ed282861acf95c72bcdc86cd4482fb
Author: Donald Haase <qu...@ya...>
Date: Sun Jul 9 13:16:33 2023 -0400
Apply suggestions from code review
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit aae7c86cf74794ac62649ba561339bd26c49108f
Author: Donald Haase <qu...@ya...>
Date: Sun Jul 9 13:10:06 2023 -0400
Update kernel/arch/dreamcast/include/arch/memory.h
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit 5c3056cc35bae9c3d9a1995a40f4017043f6324b
Author: Donald Haase <qu...@co...>
Date: Sun Jun 25 06:19:27 2023 -0400
Add changes to the maple file defines
commit aabf6aff6323133b866e2ef6f2bdb58f0ffdc270
Author: Donald Haase <qu...@co...>
Date: Sun Jun 25 05:46:16 2023 -0400
Update define name to the more descriptive SQ_BASE
commit f86a371c1c3914c051b7fbfb153ef3b500063cdf
Author: Donald Haase <qu...@co...>
Date: Sun Jun 25 05:45:06 2023 -0400
Move and rename memory header, adjust names, and expand contents.
commit 46916200b63805cecbe11bf4d71be96d2957edec
Author: Donald Haase <qu...@ya...>
Date: Tue Jun 20 11:42:36 2023 -0400
Update kernel/arch/dreamcast/include/dc/memmap.h
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit 1dc4d3ceca30cb38e25eed13f04acadcdc495732
Author: Donald Haase <qu...@ya...>
Date: Tue Jun 20 11:42:30 2023 -0400
Update kernel/arch/dreamcast/include/dc/memmap.h
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit bce717cedbb90835d235e77045a887aa68ed0c06
Author: Donald Haase <qu...@ya...>
Date: Tue Jun 20 11:42:13 2023 -0400
Update kernel/arch/dreamcast/include/dc/memmap.h
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit 4b5f505678db224d321119b2c76c6f6dbdd86699
Author: Donald Haase <qu...@ya...>
Date: Tue Jun 20 11:42:00 2023 -0400
Update kernel/arch/dreamcast/include/dc/memmap.h
Co-authored-by: Lawrence Sebald <ljs...@us...>
commit 4c603aeda21453af1429951cfe9a74e639aec7fb
Author: Donald Haase <qu...@co...>
Date: Sat Jun 10 00:33:11 2023 -0400
kos/thd WAS being used
commit bac9fcdfbab18a2ec8166c0f2b803a17bcb6f224
Author: Donald Haase <qu...@co...>
Date: Sat Jun 10 00:25:13 2023 -0400
A few more mem defines I'd missed
commit c5dd226e2d16c95c3576c221867d9858dfe7db65
Author: Donald Haase <qu...@co...>
Date: Sat Jun 10 00:21:02 2023 -0400
Adding a header for defines related to memory regions, then applying them
-----------------------------------------------------------------------
Summary of changes:
include/kos.h | 1 +
.../dreamcast/hardware/maple/maple_init_shutdown.c | 5 +-
kernel/arch/dreamcast/hardware/maple/maple_queue.c | 5 +-
kernel/arch/dreamcast/hardware/maple/maple_utils.c | 3 +-
kernel/arch/dreamcast/hardware/sq.c | 21 +-
kernel/arch/dreamcast/include/arch/memory.h | 206 ++++++++++
kernel/arch/dreamcast/include/dc/pvr.h | 3 +-
kernel/arch/dreamcast/kernel/init.c | 5 +-
utils/dc-chain/README.md | 435 ++++++++++-----------
utils/dc-chain/config/README.md | 16 +
.../config.mk.10.5.0.sample} | 109 +++---
.../config.mk.11.4.0.sample} | 109 +++---
.../config.mk.12.3.0.sample} | 109 +++---
.../config.mk.9.3.0.sample} | 103 +++--
.../config.mk.devel.sample} | 129 +++---
.../dc-chain/{ => config}/config.mk.legacy.sample | 102 +++--
.../config.mk.stable.sample} | 107 +++--
utils/dc-chain/doc/CONTRIBUTORS.md | 1 +
utils/dc-chain/doc/changelog.txt | 175 +++++++++
utils/dc-chain/docker/Dockerfile | 10 +-
.../{gcc-13.2.0-kos.diff => gcc-10.5.0-kos.diff} | 90 +++--
.../{gcc-13.1.0-kos.diff => gcc-11.4.0-kos.diff} | 90 +++--
.../{gcc-13.2.0-kos.diff => gcc-12.3.0-kos.diff} | 90 +++--
.../{gcc-13.1.0-kos.diff => gcc-devel-kos.diff} | 50 +--
24 files changed, 1170 insertions(+), 804 deletions(-)
create mode 100644 kernel/arch/dreamcast/include/arch/memory.h
create mode 100644 utils/dc-chain/config/README.md
copy utils/dc-chain/{config.mk.testing.sample => config/config.mk.10.5.0.sample} (81%)
copy utils/dc-chain/{config.mk.testing.sample => config/config.mk.11.4.0.sample} (81%)
copy utils/dc-chain/{config.mk.testing.sample => config/config.mk.12.3.0.sample} (81%)
rename utils/dc-chain/{config.mk.stable.sample => config/config.mk.9.3.0.sample} (82%)
copy utils/dc-chain/{config.mk.testing.sample => config/config.mk.devel.sample} (77%)
rename utils/dc-chain/{ => config}/config.mk.legacy.sample (80%)
rename utils/dc-chain/{config.mk.testing.sample => config/config.mk.stable.sample} (82%)
create mode 100644 utils/dc-chain/doc/changelog.txt
copy utils/dc-chain/patches/{gcc-13.2.0-kos.diff => gcc-10.5.0-kos.diff} (59%)
copy utils/dc-chain/patches/{gcc-13.1.0-kos.diff => gcc-11.4.0-kos.diff} (59%)
copy utils/dc-chain/patches/{gcc-13.2.0-kos.diff => gcc-12.3.0-kos.diff} (59%)
copy utils/dc-chain/patches/{gcc-13.1.0-kos.diff => gcc-devel-kos.diff} (69%)
diff --git a/include/kos.h b/include/kos.h
index cc072b5..9df1bbd 100644
--- a/include/kos.h
+++ b/include/kos.h
@@ -72,6 +72,7 @@ __BEGIN_DECLS
#ifdef _arch_dreamcast
# include <arch/gdb.h>
# include <arch/mmu.h>
+# include <arch/memory.h>
# include <dc/asic.h>
# include <dc/biosfont.h>
diff --git a/kernel/arch/dreamcast/hardware/maple/maple_init_shutdown.c b/kernel/arch/dreamcast/hardware/maple/maple_init_shutdown.c
index 11dc8f4..d8aab34 100644
--- a/kernel/arch/dreamcast/hardware/maple/maple_init_shutdown.c
+++ b/kernel/arch/dreamcast/hardware/maple/maple_init_shutdown.c
@@ -7,6 +7,7 @@
#include <malloc.h>
#include <stdio.h>
#include <assert.h>
+#include <arch/memory.h>
#include <dc/maple.h>
#include <dc/asic.h>
#include <dc/vblank.h>
@@ -69,7 +70,7 @@ int maple_hw_init(void) {
assert_msg((((uint32)maple_state.dma_buffer) & 0x1f) == 0, "DMA buffer was unaligned; bug in dlmalloc; please report!");
/* Force it into the P2 area */
- maple_state.dma_buffer = (uint8*)((((uint32)maple_state.dma_buffer) & 0x1fffffff) | 0xa0000000);
+ maple_state.dma_buffer = (uint8*)((((uint32)maple_state.dma_buffer) & MEM_AREA_CACHE_MASK) | MEM_AREA_P2_BASE);
#if MAPLE_DMA_DEBUG
maple_state.dma_buffer += 512;
maple_sentinel_setup(maple_state.dma_buffer - 512, MAPLE_DMA_SIZE + 1024);
@@ -124,7 +125,7 @@ void maple_hw_shutdown(void) {
#if MAPLE_DMA_DEBUG
ptr -= 512;
#endif
- ptr = (ptr & 0x1fffffff) | 0x80000000;
+ ptr = (ptr & MEM_AREA_CACHE_MASK) | MEM_AREA_P1_BASE;
free((void *)ptr);
maple_state.dma_buffer = NULL;
}
diff --git a/kernel/arch/dreamcast/hardware/maple/maple_queue.c b/kernel/arch/dreamcast/hardware/maple/maple_queue.c
index 0712f8e..6566a75 100644
--- a/kernel/arch/dreamcast/hardware/maple/maple_queue.c
+++ b/kernel/arch/dreamcast/hardware/maple/maple_queue.c
@@ -10,6 +10,7 @@
#include <string.h>
#include <dc/maple.h>
#include <arch/irq.h>
+#include <arch/memory.h>
/* Send all queued frames */
void maple_queue_flush(void) {
@@ -44,7 +45,7 @@ void maple_queue_flush(void) {
*out++ = i->length | (i->dst_port << 16);
/* Second word: receive buffer physical address */
- *out++ = ((uint32)i->recv_buf) & 0x1fffffff;
+ *out++ = ((uint32)i->recv_buf) & MEM_AREA_CACHE_MASK;
/* Third word: command, addressing, packet length */
*out++ = (i->cmd & 0xff) | (maple_addr(i->dst_port, i->dst_unit) << 8)
@@ -157,7 +158,7 @@ void maple_frame_init(maple_frame_t *frame) {
#if MAPLE_DMA_DEBUG
buf_ptr += 512;
#endif
- buf_ptr = (buf_ptr & 0x1fffffff) | 0xa0000000;
+ buf_ptr = (buf_ptr & MEM_AREA_CACHE_MASK) | MEM_AREA_P2_BASE;
frame->recv_buf = (uint8*)buf_ptr;
/* Clear out the receive buffer */
diff --git a/kernel/arch/dreamcast/hardware/maple/maple_utils.c b/kernel/arch/dreamcast/hardware/maple/maple_utils.c
index da38c2a..a720404 100644
--- a/kernel/arch/dreamcast/hardware/maple/maple_utils.c
+++ b/kernel/arch/dreamcast/hardware/maple/maple_utils.c
@@ -8,6 +8,7 @@
#include <assert.h>
#include <stdio.h>
#include <string.h>
+#include <arch/memory.h>
#include <dc/maple.h>
/* Enable / Disable the bus */
@@ -32,7 +33,7 @@ int maple_dma_in_progress(void) {
/* Set the DMA Address */
void maple_dma_addr(void *ptr) {
- maple_write(MAPLE_DMAADDR, ((uint32) ptr) & 0x1fffffff);
+ maple_write(MAPLE_DMAADDR, ((uint32) ptr) & MEM_AREA_CACHE_MASK);
}
/* Return a "maple address" for a port,unit pair */
diff --git a/kernel/arch/dreamcast/hardware/sq.c b/kernel/arch/dreamcast/hardware/sq.c
index c6c89d4..4ec7be3 100644
--- a/kernel/arch/dreamcast/hardware/sq.c
+++ b/kernel/arch/dreamcast/hardware/sq.c
@@ -4,6 +4,7 @@
Copyright (C) 2001 Andrew Kieschnick
*/
+#include <arch/memory.h>
#include <dc/sq.h>
/*
@@ -15,7 +16,7 @@
/* clears n bytes at dest, dest must be 32-byte aligned */
void sq_clr(void *dest, int n) {
unsigned int *d = (unsigned int *)(void *)
- (0xe0000000 | (((unsigned long)dest) & 0x03ffffe0));
+ (MEM_AREA_SQ_BASE | (((unsigned long)dest) & 0x03ffffe0));
/* Set store queue memory area as desired */
QACR0 = ((((unsigned int)dest) >> 26) << 2) & 0x1c;
@@ -34,14 +35,14 @@ void sq_clr(void *dest, int n) {
}
/* Wait for both store queues to complete */
- d = (unsigned int *)0xe0000000;
+ d = (unsigned int *)MEM_AREA_SQ_BASE;
d[0] = d[8] = 0;
}
/* copies n bytes from src to dest, dest must be 32-byte aligned */
void * sq_cpy(void *dest, const void *src, int n) {
unsigned int *d = (unsigned int *)(void *)
- (0xe0000000 | (((unsigned long)dest) & 0x03ffffe0));
+ (MEM_AREA_SQ_BASE | (((unsigned long)dest) & 0x03ffffe0));
const unsigned int *s = src;
/* Set store queue memory area as desired */
@@ -66,7 +67,7 @@ void * sq_cpy(void *dest, const void *src, int n) {
}
/* Wait for both store queues to complete */
- d = (unsigned int *)0xe0000000;
+ d = (unsigned int *)MEM_AREA_SQ_BASE;
d[0] = d[8] = 0;
return dest;
@@ -75,7 +76,7 @@ void * sq_cpy(void *dest, const void *src, int n) {
/* fills n bytes at s with byte c, s must be 32-byte aligned */
void * sq_set(void *s, uint32 c, int n) {
unsigned int *d = (unsigned int *)(void *)
- (0xe0000000 | (((unsigned long)s) & 0x03ffffe0));
+ (MEM_AREA_SQ_BASE | (((unsigned long)s) & 0x03ffffe0));
/* Set store queue memory area as desired */
QACR0 = ((((unsigned int)s) >> 26) << 2) & 0x1c;
@@ -98,7 +99,7 @@ void * sq_set(void *s, uint32 c, int n) {
}
/* Wait for both store queues to complete */
- d = (unsigned int *)0xe0000000;
+ d = (unsigned int *)MEM_AREA_SQ_BASE;
d[0] = d[8] = 0;
return s;
@@ -107,7 +108,7 @@ void * sq_set(void *s, uint32 c, int n) {
/* fills n bytes at s with short c, s must be 32-byte aligned */
void * sq_set16(void *s, uint32 c, int n) {
unsigned int *d = (unsigned int *)(void *)
- (0xe0000000 | (((unsigned long)s) & 0x03ffffe0));
+ (MEM_AREA_SQ_BASE | (((unsigned long)s) & 0x03ffffe0));
/* Set store queue memory area as desired */
QACR0 = ((((unsigned int)s) >> 26) << 2) & 0x1c;
@@ -130,7 +131,7 @@ void * sq_set16(void *s, uint32 c, int n) {
}
/* Wait for both store queues to complete */
- d = (unsigned int *)0xe0000000;
+ d = (unsigned int *)MEM_AREA_SQ_BASE;
d[0] = d[8] = 0;
return s;
@@ -139,7 +140,7 @@ void * sq_set16(void *s, uint32 c, int n) {
/* fills n bytes at s with int c, s must be 32-byte aligned */
void * sq_set32(void *s, uint32 c, int n) {
unsigned int *d = (unsigned int *)(void *)
- (0xe0000000 | (((unsigned long)s) & 0x03ffffe0));
+ (MEM_AREA_SQ_BASE | (((unsigned long)s) & 0x03ffffe0));
/* Set store queue memory area as desired */
QACR0 = ((((unsigned int)s) >> 26) << 2) & 0x1c;
@@ -158,7 +159,7 @@ void * sq_set32(void *s, uint32 c, int n) {
}
/* Wait for both store queues to complete */
- d = (unsigned int *)0xe0000000;
+ d = (unsigned int *)MEM_AREA_SQ_BASE;
d[0] = d[8] = 0;
return s;
diff --git a/kernel/arch/dreamcast/include/arch/memory.h b/kernel/arch/dreamcast/include/arch/memory.h
new file mode 100644
index 0000000..9a19124
--- /dev/null
+++ b/kernel/arch/dreamcast/include/arch/memory.h
@@ -0,0 +1,206 @@
+/* KallistiOS ##version##
+
+ kernel/arch/dreamcast/include/arch/memory.h
+ Copyright (C) 2023 Donald Haase
+
+*/
+
+/** \file arch/memory.h
+ \brief Constants for areas of the system memory map.
+
+ Various addresses and masks that are set by the SH7750. None of the values
+ here are Dreamcast-specific.
+
+ These values are drawn from the Hitatchi SH7750 Series Hardware Manual rev 6.0.
+
+ \author Donald Haase
+*/
+
+#ifndef __ARCH_MEMORY_H
+#define __ARCH_MEMORY_H
+
+#include <sys/cdefs.h>
+__BEGIN_DECLS
+
+/** \defgroup memory Memory
+ \brief Basics of the SH4 Memory Map
+
+ The SH7750 Series physical address space is mapped onto a 29-bit external
+ memory space, with the upper 3 bits of the address indicating which memory
+ region will be used. The P0/U0 memory region spans a 2GB space with the
+ bottom 512MB mirrored to the P1, P2, and P3 regions.
+
+*/
+
+/** \brief Mask a cache-agnostic address.
+ \ingroup memory
+
+ This masks out the upper 3 bits of an address. This is used when it is
+ necssary to access memory with a specified caching mode. This is needed for
+ DMA and SQ usage as well as various MMU functions.
+
+*/
+#define MEM_AREA_CACHE_MASK 0x1fffffff
+
+/** \brief U0 memory region (cachable).
+ \ingroup memory
+
+ This is the base user mode memory address. It is cacheable as determined
+ by the WT bit of the cache control register. By default KOS sets this to
+ copy-back mode.
+
+ KOS runs in privileged mode, so this is here merely for completeness.
+
+*/
+#define MEM_AREA_U0_BASE 0x00000000
+
+/** \brief P0 memory region (cachable).
+ \ingroup memory
+
+ This is the base privileged mode memory address. It is cacheable as determined
+ by the WT bit of the cache control register. By default KOS sets this to
+ copy-back mode.
+
+*/
+#define MEM_AREA_P0_BASE 0x00000000
+
+/** \brief P1 memory region (cachable).
+ \ingroup memory
+
+ This is a modularly cachable memory region. It is cacheable as determined by
+ the CB bit of the cache control register. That allows it to function in a
+ different caching mode (copy-back v write-through) than the U0, P0, and P3
+ regions, whose cache mode are governed by the WT bit. By default KOS sets this
+ to the same copy-back mode as the other cachable regions.
+
+*/
+#define MEM_AREA_P1_BASE 0x80000000
+
+/** \brief P2 memory region (non-cachable).
+ \ingroup memory
+
+ This is the non-cachable memory region. It is most frequently for DMA
+ transactions to ensure reads are not cached.
+
+*/
+#define MEM_AREA_P2_BASE 0xa0000000
+
+/** \brief P3 memory region (cachable).
+ \ingroup memory
+
+ This functions as the lower 512MB of P0.
+
+*/
+#define MEM_AREA_P3_BASE 0xc0000000
+
+/** \brief P4 SH-internal memory region (non-cachable).
+ \defgroup p4mem
+ \ingroup memory
+
+ This offset maps to on-chip I/O channels.
+
+*/
+#define MEM_AREA_P4_BASE 0xe0000000
+
+/** \brief Store Queue (SQ) memory base.
+ \ingroup p4mem
+
+ This offset maps to the SQ memory region. RW to addresses from
+ 0xe0000000-0xe3ffffff follow SQ rules.
+
+ \see dc\sq.h
+
+*/
+#define MEM_AREA_SQ_BASE 0xe0000000
+
+/** \brief Instruction cache address array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the instruction cache address array.
+
+*/
+#define MEM_AREA_ICACHE_ADDRESS_ARRAY_BASE 0xf0000000
+
+/** \brief Instruction cache data array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the instruction cache data array.
+
+*/
+#define MEM_AREA_ICACHE_DATA_ARRAY_BASE 0xf1000000
+
+/** \brief Instruction TLB address array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the instruction TLB address array.
+
+*/
+#define MEM_AREA_ITLB_ADDRESS_ARRAY_BASE 0xf2000000
+
+/** \brief Instruction TLB data array 1 base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the instruction TLB data array 1.
+
+*/
+#define MEM_AREA_ITLB_DATA_ARRAY1_BASE 0xf3000000
+
+/** \brief Instruction TLB data array 2 base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the instruction TLB data array 2.
+
+*/
+#define MEM_AREA_ITLB_DATA_ARRAY2_BASE 0xf3800000
+
+/** \brief Operand cache address array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the operand cache address array.
+
+*/
+#define MEM_AREA_OCACHE_ADDRESS_ARRAY_BASE 0xf4000000
+
+/** \brief Instruction cache data array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the operand cache data array.
+
+*/
+#define MEM_AREA_OCACHE_DATA_ARRAY_BASE 0xf5000000
+
+/** \brief Unified TLB address array base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the unified TLB address array.
+
+*/
+#define MEM_AREA_UTLB_ADDRESS_ARRAY_BASE 0xf6000000
+
+/** \brief Unified TLB data array 1 base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the unified TLB data array 1.
+
+*/
+#define MEM_AREA_UTLB_DATA_ARRAY1_BASE 0xf7000000
+
+/** \brief Unified TLB data array 2 base.
+ \ingroup p4mem
+
+ This offset is used for direct access to the unified TLB data array 2.
+
+*/
+#define MEM_AREA_UTLB_DATA_ARRAY2_BASE 0xf7800000
+
+/** \brief Control Register base.
+ \ingroup p4mem
+
+ This is the base address of all control registers
+
+*/
+#define MEM_AREA_CTRL_REG_BASE 0xff000000
+
+__END_DECLS
+
+#endif /* __ARCH_MEMORY_H */
diff --git a/kernel/arch/dreamcast/include/dc/pvr.h b/kernel/arch/dreamcast/include/dc/pvr.h
index e332ab1..d3efe2d 100644
--- a/kernel/arch/dreamcast/include/dc/pvr.h
+++ b/kernel/arch/dreamcast/include/dc/pvr.h
@@ -34,6 +34,7 @@
#include <sys/cdefs.h>
__BEGIN_DECLS
+#include <arch/memory.h>
#include <arch/types.h>
#include <dc/sq.h>
#include <kos/img.h>
@@ -1662,7 +1663,7 @@ typedef uint32 pvr_dr_state_t;
*/
#define pvr_dr_target(vtx_buf_ptr) \
({ (vtx_buf_ptr) ^= 32; \
- (pvr_vertex_t *)(0xe0000000 | (vtx_buf_ptr)); \
+ (pvr_vertex_t *)(MEM_AREA_P4_MASK | (vtx_buf_ptr)); \
})
/** \brief Commit a primitive written into the Direct Rendering target address.
diff --git a/kernel/arch/dreamcast/kernel/init.c b/kernel/arch/dreamcast/kernel/init.c
index 86badbe..82373b5 100644
--- a/kernel/arch/dreamcast/kernel/init.c
+++ b/kernel/arch/dreamcast/kernel/init.c
@@ -10,10 +10,11 @@
#include <string.h>
#include <stdlib.h>
#include <kos/dbgio.h>
-#include <arch/timer.h>
#include <arch/arch.h>
#include <arch/irq.h>
+#include <arch/memory.h>
#include <arch/rtc.h>
+#include <arch/timer.h>
#include <dc/ubc.h>
#include <dc/pvr.h>
#include <dc/vmufs.h>
@@ -378,6 +379,6 @@ void arch_reboot(void) {
irq_disable();
/* Reboot */
- rb = (reboot_func)0xa0000000;
+ rb = (reboot_func)(MEM_AREA_P2_BASE | 0x00000000);
rb();
}
diff --git a/utils/dc-chain/README.md b/utils/dc-chain/README.md
index d627b98..6a8b897 100644
--- a/utils/dc-chain/README.md
+++ b/utils/dc-chain/README.md
@@ -1,88 +1,87 @@
# Sega Dreamcast Toolchains Maker (`dc-chain`)
-The **Sega Dreamcast Toolchains Maker** (`dc-chain`) utility is a set of files
-made for building all the needed toolchains used in **Sega Dreamcast**
-programming under the **KallistiOS** environment. It was first released by
-*Jim Ursetto* back in 2004 and was initially adapted from *Stalin*'s build
-script v0.3. This utility is part of **KallistiOS** (**KOS**).
-
-By using this utility, 2 toolchains will be built for **Dreamcast** development:
-
-- A `sh-elf` toolchain, which is the main toolchain as it targets the CPU of the
- **Dreamcast**, i.e. the **Hitachi SH-4 CPU** (a.k.a. **SuperH**).
-- An `arm-eabi` toolchain, which is the toolchain used only for the **Yamaha
- Super Intelligent Sound Processor** (**AICA**). This processor is based
- on an **ARM7** core. Under **KallistiOS**, only the sound driver is compiled
...<truncated>...
hooks/post-receive
--
A pseudo Operating System for the Dreamcast.
|
