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[cadcdev-svn-commits] [SCM] branch master updated. v2.0.0-726-gb65b96f
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From: ljsebald <ljs...@us...> - 2023-04-01 01:08:42
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- Log -----------------------------------------------------------------
commit b65b96f95855f2b018552ce9ea5f2aacfca5fdb7
Merge: 809e2e1 16a44ff
Author: Lawrence Sebald <ljs...@us...>
Date: Fri Mar 31 21:04:24 2023 -0400
Merge pull request #140 from Dreamcast-Projects/master
Make sure clearing a counter stops it first. Updated read me to inclâ¦
commit 809e2e1ebfa89eb14d3defd9efd4420a6b7fada9
Merge: 8017df8 c7d13b6
Author: Lawrence Sebald <ljs...@us...>
Date: Fri Mar 31 21:03:15 2023 -0400
Merge pull request #141 from KallistiOS/cpp_time
Update kos/time.h header for C++ support
commit 16a44ff18ca0b02ce1ec0f9f0ada23f99001197d
Author: Andress Barajas <and...@gm...>
Date: Fri Mar 31 16:35:07 2023 -0700
Added better doxygen documentation for performance counters
commit 53df25d6fc9ad34e5f8e5adb26934dc80eb1171e
Author: Andress Barajas <and...@gm...>
Date: Fri Mar 31 16:15:38 2023 -0700
Added documentation inside the comments
commit 2141d3e92afac0daf78278461da2af2c1e3931db
Author: Andress Barajas <and...@gm...>
Date: Fri Mar 31 13:25:12 2023 -0700
Make sure clearing a counter stops it first. Updated read me to include performance counters. Fixed a comment
-----------------------------------------------------------------------
Summary of changes:
README.md | 2 +-
doc/CHANGELOG | 1 +
include/kos/time.h | 6 +-
kernel/arch/dreamcast/include/arch/timer.h | 106 ++++++++++++++++++-----------
kernel/arch/dreamcast/kernel/timer.c | 5 +-
5 files changed, 73 insertions(+), 47 deletions(-)
diff --git a/README.md b/README.md
index 90f69cf..c03f033 100644
--- a/README.md
+++ b/README.md
@@ -23,7 +23,7 @@ Despite the console's age, KOS offers an extremely modern, programmer-friendly d
* Flashrom Access
* AICA SPU Sound Processor Driver
* Cache and Store Queue Management
-* Timer Peripherals and Real-Time Clock
+* Timer Peripherals, Real-Time Clock, Performance Counters
* MMU Management API
* BIOS Font Rendering
diff --git a/doc/CHANGELOG b/doc/CHANGELOG
index 8de8b48..46929d8 100644
--- a/doc/CHANGELOG
+++ b/doc/CHANGELOG
@@ -158,6 +158,7 @@ KallistiOS version 2.1.0 -----------------------------------------------
- *** Removed (completely unsupported) support for GCC 3.x and older [LS]
- *** Add timespec_get C11 function to koslib's libc [LS]
- DC Added timer_ns_gettime64() and performance counters [AB]
+- *** Added check to allow strict C++17+ to use timespec_get [FG]
KallistiOS version 2.0.0 -----------------------------------------------
- DC Broadband Adapter driver fixes [Dan Potter == DP]
diff --git a/include/kos/time.h b/include/kos/time.h
index 78279b5..d32da92 100644
--- a/include/kos/time.h
+++ b/include/kos/time.h
@@ -14,7 +14,7 @@
#ifndef __KOS_TIME_H
#define __KOS_TIME_H
-#if !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 201112L)
+#if !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 201112L) || (__cplusplus >= 201703L)
#include <kos/cdefs.h>
@@ -29,5 +29,5 @@ extern int timespec_get(struct timespec *ts, int base);
__END_DECLS
-#endif /* !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 201112L) */
-#endif /* !__KOS_C11TIME_H */
+#endif /* !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 201112L) || (__cplusplus >= 201703L) */
+#endif /* !__KOS_TIME_H */
diff --git a/kernel/arch/dreamcast/include/arch/timer.h b/kernel/arch/dreamcast/include/arch/timer.h
index 4286cf1..ffbb74a 100644
--- a/kernel/arch/dreamcast/include/arch/timer.h
+++ b/kernel/arch/dreamcast/include/arch/timer.h
@@ -225,72 +225,91 @@ int timer_init();
void timer_shutdown();
/* \endcond */
+/** \defgroup perf_counters Performance Counters
+ The performance counter API exposes the SH4's hardware profiling registers,
+ which consist of two different sets of independently operable 64-bit
+ counters.
+*/
+
/** \brief SH4 Performance Counter.
+ \ingroup perf_counters
This counter is used by the ns_gettime function in this header.
*/
#define PRFC0 0
/** \brief SH4 Performance Counter.
+ \ingroup perf_counters
A counter that is not used by KOS.
*/
#define PRFC1 1
-/** \brief CPU Cycles Count Type
+/** \brief CPU Cycles Count Type.
+ \ingroup perf_counters
Count cycles. At 5 ns increments, a 48-bit cycle counter can
run continuously for 16.33 days.
*/
#define PMCR_COUNT_CPU_CYCLES 0
-/** \brief Ratio Cycles Count Type
+/** \brief Ratio Cycles Count Type.
+ \ingroup perf_counters
CPU/bus ratio mode where cycles (where T = C x B / 24 and T is time,
C is count, and B is time of one bus cycle).
*/
#define PMCR_COUNT_RATIO_CYCLES 1
+/** \defgroup perf_counters_modes Performance Counter Modes
+ This is the list of modes that are allowed to be passed into the perf_cntr_start()
+ function, representing different things you want to count.
+ \ingroup perf_counters
+ @{
+*/
/* MODE DEFINITION VALUE MEASURMENT TYPE & NOTES */
-#define PMCR_INIT_NO_MODE 0x00 /* None; Just here to be complete */
-#define PMCR_OPERAND_READ_ACCESS_MODE 0x01 /* Quantity; With cache */
-#define PMCR_OPERAND_WRITE_ACCESS_MODE 0x02 /* Quantity; With cache */
-#define PMCR_UTLB_MISS_MODE 0x03 /* Quantity */
-#define PMCR_OPERAND_CACHE_READ_MISS_MODE 0x04 /* Quantity */
-#define PMCR_OPERAND_CACHE_WRITE_MISS_MODE 0x05 /* Quantity */
-#define PMCR_INSTRUCTION_FETCH_MODE 0x06 /* Quantity; With cache */
-#define PMCR_INSTRUCTION_TLB_MISS_MODE 0x07 /* Quantity */
-#define PMCR_INSTRUCTION_CACHE_MISS_MODE 0x08 /* Quantity */
-#define PMCR_ALL_OPERAND_ACCESS_MODE 0x09 /* Quantity */
-#define PMCR_ALL_INSTRUCTION_FETCH_MODE 0x0a /* Quantity */
-#define PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE 0x0b /* Quantity */
+#define PMCR_INIT_NO_MODE 0x00 /**< \brief None; Just here to be complete */
+#define PMCR_OPERAND_READ_ACCESS_MODE 0x01 /**< \brief Quantity; With cache */
+#define PMCR_OPERAND_WRITE_ACCESS_MODE 0x02 /**< \brief Quantity; With cache */
+#define PMCR_UTLB_MISS_MODE 0x03 /**< \brief Quantity */
+#define PMCR_OPERAND_CACHE_READ_MISS_MODE 0x04 /**< \brief Quantity */
+#define PMCR_OPERAND_CACHE_WRITE_MISS_MODE 0x05 /**< \brief Quantity */
+#define PMCR_INSTRUCTION_FETCH_MODE 0x06 /**< \brief Quantity; With cache */
+#define PMCR_INSTRUCTION_TLB_MISS_MODE 0x07 /**< \brief Quantity */
+#define PMCR_INSTRUCTION_CACHE_MISS_MODE 0x08 /**< \brief Quantity */
+#define PMCR_ALL_OPERAND_ACCESS_MODE 0x09 /**< \brief Quantity */
+#define PMCR_ALL_INSTRUCTION_FETCH_MODE 0x0a /**< \brief Quantity */
+#define PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE 0x0b /**< \brief Quantity */
/* No 0x0c */
-#define PMCR_ON_CHIP_IO_ACCESS_MODE 0x0d /* Quantity */
-#define PMCR_OPERAND_ACCESS_MODE 0x0e /* Quantity; With cache, counts both reads and writes */
-#define PMCR_OPERAND_CACHE_MISS_MODE 0x0f /* Quantity */
-#define PMCR_BRANCH_ISSUED_MODE 0x10 /* Quantity; Not the same as branch taken! */
-#define PMCR_BRANCH_TAKEN_MODE 0x11 /* Quantity */
-#define PMCR_SUBROUTINE_ISSUED_MODE 0x12 /* Quantity; Issued a BSR, BSRF, JSR, JSR/N */
-#define PMCR_INSTRUCTION_ISSUED_MODE 0x13 /* Quantity */
-#define PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE 0x14 /* Quantity */
-#define PMCR_FPU_INSTRUCTION_ISSUED_MODE 0x15 /* Quantity */
-#define PMCR_INTERRUPT_COUNTER_MODE 0x16 /* Quantity */
-#define PMCR_NMI_COUNTER_MODE 0x17 /* Quantity */
-#define PMCR_TRAPA_INSTRUCTION_COUNTER_MODE 0x18 /* Quantity */
-#define PMCR_UBC_A_MATCH_MODE 0x19 /* Quantity */
-#define PMCR_UBC_B_MATCH_MODE 0x1a /* Quantity */
+#define PMCR_ON_CHIP_IO_ACCESS_MODE 0x0d /**< \brief Quantity */
+#define PMCR_OPERAND_ACCESS_MODE 0x0e /**< \brief Quantity; With cache, counts both reads and writes */
+#define PMCR_OPERAND_CACHE_MISS_MODE 0x0f /**< \brief Quantity */
+#define PMCR_BRANCH_ISSUED_MODE 0x10 /**< \brief Quantity; Not the same as branch taken! */
+#define PMCR_BRANCH_TAKEN_MODE 0x11 /**< \brief Quantity */
+#define PMCR_SUBROUTINE_ISSUED_MODE 0x12 /**< \brief Quantity; Issued a BSR, BSRF, JSR, JSR/N */
+#define PMCR_INSTRUCTION_ISSUED_MODE 0x13 /**< \brief Quantity */
+#define PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE 0x14 /**< \brief Quantity */
+#define PMCR_FPU_INSTRUCTION_ISSUED_MODE 0x15 /**< \brief Quantity */
+#define PMCR_INTERRUPT_COUNTER_MODE 0x16 /**< \brief Quantity */
+#define PMCR_NMI_COUNTER_MODE 0x17 /**< \brief Quantity */
+#define PMCR_TRAPA_INSTRUCTION_COUNTER_MODE 0x18 /**< \brief Quantity */
+#define PMCR_UBC_A_MATCH_MODE 0x19 /**< \brief Quantity */
+#define PMCR_UBC_B_MATCH_MODE 0x1a /**< \brief Quantity */
/* No 0x1b-0x20 */
-#define PMCR_INSTRUCTION_CACHE_FILL_MODE 0x21 /* Cycles */
-#define PMCR_OPERAND_CACHE_FILL_MODE 0x22 /* Cycles */
-#define PMCR_ELAPSED_TIME_MODE 0x23 /* Cycles; For 200MHz CPU: 5ns per count in 1 cycle = 1 count mode, or around 417.715ps per count (increments by 12) in CPU/bus ratio mode */
-#define PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE 0x24 /* Cycles */
-#define PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE 0x25 /* Cycles */
+#define PMCR_INSTRUCTION_CACHE_FILL_MODE 0x21 /**< \brief Cycles */
+#define PMCR_OPERAND_CACHE_FILL_MODE 0x22 /**< \brief Cycles */
+#define PMCR_ELAPSED_TIME_MODE 0x23 /**< \brief Cycles; For 200MHz CPU: 5ns per count in 1 cycle = 1 count mode, or around 417.715ps per count (increments by 12) in CPU/bus ratio mode */
+#define PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE 0x24 /**< \brief Cycles */
+#define PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE 0x25 /**< \brief Cycles */
/* No 0x26 */
-#define PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE 0x27 /* Cycles */
-#define PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE 0x28 /* Cycles */
-#define PMCR_PIPELINE_FREEZE_BY_FPU_MODE 0x29 /* Cycles */
+#define PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE 0x27 /**< \brief Cycles */
+#define PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE 0x28 /**< \brief Cycles */
+#define PMCR_PIPELINE_FREEZE_BY_FPU_MODE 0x29 /**< \brief Cycles */
+/** @} */
+
/** \brief Get a performance counter's settings.
+ \ingroup perf_counters
This function returns a performance counter's settings.
@@ -300,6 +319,7 @@ void timer_shutdown();
uint16 perf_cntr_get_config(int which);
/** \brief Start a performance counter.
+ \ingroup perf_counters
This function starts a performance counter
@@ -311,6 +331,7 @@ uint16 perf_cntr_get_config(int which);
int perf_cntr_start(int which, int mode, int count_type);
/** \brief Stop a performance counter.
+ \ingroup perf_counters
This function stops a performance counter that was started with perf_cntr_start().
Stopping a counter retains its count. To clear the count use perf_cntr_clear().
@@ -320,11 +341,12 @@ int perf_cntr_start(int which, int mode, int count_type);
*/
int perf_cntr_stop(int which);
-/** \brief Clear a performance counter
+/** \brief Clear a performance counter.
+ \ingroup perf_counters
- This function clears a performance counter. It resets its value to zero.
- You cannot clear a running counter. This function stops the counter before
- clearing it because you cant clear a running counter.
+ This function clears a performance counter. It resets its count to zero.
+ This function stops the counter before clearing it because you cant clear
+ a running counter.
\param which The counter to clear (i.e, \ref PRFC0 or PRFC1).
\retval 0 On success.
@@ -332,6 +354,7 @@ int perf_cntr_stop(int which);
int perf_cntr_clear(int which);
/** \brief Obtain the count of a performance counter.
+ \ingroup perf_counters
This function simply returns the count of the counter.
@@ -341,6 +364,7 @@ int perf_cntr_clear(int which);
uint64 perf_cntr_count(int which);
/** \brief Enable the nanosecond timer.
+ \ingroup perf_counters
This function enables the performance counter used for the timer_ns_gettime64()
function. This is on by default. The function uses \ref PRFC0 to do the work.
@@ -348,6 +372,7 @@ uint64 perf_cntr_count(int which);
void timer_ns_enable();
/** \brief Disable the nanosecond timer.
+ \ingroup perf_counters
This function disables the performance counter used for the timer_ns_gettime64()
function. Generally, you will not want to do this, unless you have some need to use
@@ -356,6 +381,7 @@ void timer_ns_enable();
void timer_ns_disable();
/** \brief Get the current uptime of the system (in nanoseconds).
+ \ingroup perf_counters
This function retrieves the number of nanoseconds since KOS was started.
diff --git a/kernel/arch/dreamcast/kernel/timer.c b/kernel/arch/dreamcast/kernel/timer.c
index 3829781..ecc7a34 100644
--- a/kernel/arch/dreamcast/kernel/timer.c
+++ b/kernel/arch/dreamcast/kernel/timer.c
@@ -337,7 +337,6 @@ uint16 perf_cntr_get_config(int which) {
/* Start a performance counter */
int perf_cntr_start(int which, int mode, int count_type) {
- perf_cntr_stop(which);
perf_cntr_clear(which);
PMCR_CTRL(which) = PMCR_RUN | mode | (count_type << PMCR_CLOCK_TYPE_SHIFT);
@@ -351,8 +350,9 @@ int perf_cntr_stop(int which) {
return 0;
}
-/* Clears a performance counter */
+/* Clears a performance counter. Has to stop it first. */
int perf_cntr_clear(int which) {
+ perf_cntr_stop(which);
PMCR_CTRL(which) |= PMCR_CLR;
return 0;
@@ -372,7 +372,6 @@ void timer_ns_disable() {
/* If timer is running, disable it */
if((config & PMCR_ELAPSED_TIME_MODE)) {
- perf_cntr_stop(PRFC0);
perf_cntr_clear(PRFC0);
}
}
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A pseudo Operating System for the Dreamcast.
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