RE: [Bochs-developers] Bug in bochs cmpxchg

[Christopher N. <paradox@BBHC.ORG>]

Interesting.  I looked carefully at the instruction exceptions page, and
it doesn't list the #UD exception.  But when I look at the lock
instruction, it lists that there.  Bizarre.  Oh well! Thanks for your
help!  I changed the reference to be a register/memory and it was fine.
Thanks again!

-=3D{C}=3D-

> I guess in your code. Intel documentation says:
>=20
>  The  LOCK  prefix  can be prepended * only to the following=20
> instructions *  and  * only  to  those  forms  of the=20
> instructions where the destination  operand  is  a  memory=20
> operand * : ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,  CMPXCH8B,=20
>  DEC,  INC,  NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If =20
> the  LOCK prefix is used with one of these instructions and=20
> the source  operand  is a memory operand, an undefined opcode=20
> exception (#UD) will  be  generated. An undefined opcode=20
> exception will also be generated if  the  LOCK  prefix  is=20
> used with any instruction not in the above list.
>  The XCHG instruction always asserts the LOCK# signal=20
> regardless of the  presence or absence of the LOCK prefix.
>=20
> According to this description LOCK prefix definitely not=20
> allowed for CMPXCHG instruction when mod=3D0xc0. Read carefully=20
> * selected comments *.
>=20
> Stanislav
>=20
> -----Original Message-----
> From: boc...@li...
> [mailto:boc...@li...] On=20
> Behalf Of Christopher Nelson
> Sent: Monday, December 19, 2005 7:20 PM
> To: boc...@li...
> Subject: [Bochs-developers] Bug in bochs cmpxchg
>=20
> When running bochs, I get an exception:
>=20
> LOCK prefix unallowed (op1=3D0x1b1, attr=3D0x300, mod=3D0xc0, nnn=3D2)
>=20
> This decodes to cmpxchg.  The intel instruction set manual=20
> specifically states that this instruction may be used with=20
> the LOCK prefix. =20
>=20
> Where do I fix this?
>=20
> -=3D{C}=3D-
>=20
>=20
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