Artifacts exist with the emulated PICs (also APIC) which lead to non accurate behaviour.
It may be desirable to introduce delays to better model the platform hardware.
Specific case (there may be others, this is merely an example) : in Bochs, when PIC receives
an eligible interrupt request, it passes from the IRR to the ISR instantaneously (as far as the emulated
CPU is aware) : unlike on real platforms, Bochs CPU doesn't get a chance to "see" the request coming into IRR
(reading IRR from the foreground program will always yield zero in Bochs unlike real ISA).
Is this by design, or shouldn't Bochs be designed to let the CPU(s) execute in (quasi)parallelism with
the PICs ?
Similar remarks might apply to other elements of the platform or "chipset" which are running in
parallel, but I'll limit this artefact report to the PIC for definiteness, and because I stumbled on
this case accidentally...
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