#1300 UHCI PCI interrupts

fixed_in_SVN
closed
5
2012-10-15
2012-06-08
Piotrek
No

UHCI PCI device does not set low its PCI interrupt line immediately after clearing bits in UHCI STATUS register. Instead, the PCI interrupt line is kept high until the next end of frame (EOF).

Discussion

  • Volker Ruppert

    Volker Ruppert - 2012-06-17

    UHCI IRQ fixes and improvements (ported from Qemu) are present in SVN now. Can you confirm that it works as expected?

     
  • Piotrek

    Piotrek - 2012-06-21

    Well, I've checked this new implementation and it solves the problem. Nonetheless, there is another problem. If the UHCI IRQ is not serviced until the end of the next frame, it is cleared. This should not happen. See this debug output:

    00219460000d[UHCI ] Queue 0: 0x00030280 1 0 0x00030650 1 0
    00219460000d[UHCI ] Queue 1: 0x00030280 1 0 0x00030740 0 0
    00219460000d[UHCI ] Frame: 0551 (0x0227)
    00219460000d[UHCI ] QH002:TD found at address: 0x00030740
    00219460000d[UHCI ] 00000001 1D800000 00E08169 000306C4
    00219460000d[UHCI ] r_actlen = 0x0008 r_maxlen = 0x0008
    00219460000d[UHCI ] Queue 2: 0x000302C0 1 0 0x00000000 0 1
    00219460000d[UHCI ] Queue 3: 0x00030300 1 0 0x00000000 0 1
    00219460000d[UHCI ] Queue 4: 0x00000000 0 1 0x00000000 0 1
    00219460000d[UHCI ] [IOC] We want it to fire here (Frame: 0551) <-- interrupt fires, but all interrupts are disabled on CPU (cli)
    00219460000d[PIC ] IRQ line 9 now high
    00219460000d[PIC ] slave: signalling IRQ(9)
    00219460000d[PIC ] IRQ line 2 now high
    00219460000d[PIC ] signalling IRQ(2)
    00219460000d[P2I ] PIRQD -> IRQ 9 = 1
    00219470000d[UHCI ] Queue 0: 0x00030280 1 0 0x00030650 1 0
    00219470000d[UHCI ] Queue 1: 0x00030280 1 0 0x00000000 0 1
    00219470000d[UHCI ] Queue 2: 0x000302C0 1 0 0x00000000 0 1
    00219470000d[UHCI ] Queue 3: 0x00030300 1 0 0x00000000 0 1
    00219470000d[UHCI ] Queue 4: 0x00000000 0 1 0x00000000 0 1
    00219470000d[IOAP ] set_irq_level(): INTIN19: level=0
    00219470000d[IOAP ] set_irq_level(): INTIN9: level=0
    00219470000d[PIC ] IRQ line 9 now low <-- now the 9th interrupt is set to low, while it was not serviced!!! (bug in the code - usb_uhci.cc line 738)
    00219470000d[P2I ] PIRQD -> IRQ 9 = 0
    00219471311d[CPU0 ] inhibit interrupts mask = 1 <-- interrupts enabled (sti)
    00219471313d[CPU0 ] interrupt(): vector = 2f, TYPE = 0, EXT = 1 <-- interrupt at CPU, vector indicates interrupt 15 (base is 0x20) ??? Bogus interrupt
    00219471313d[CPU0 ] interrupt(): INTERRUPT TO SAME PRIVILEGE

     
  • Volker Ruppert

    Volker Ruppert - 2012-06-21

    Second try: don't clear pending interrupt bits when setting the status. Patch applied to SVN. Does everything work as expected now?

     
  • Piotrek

    Piotrek - 2012-06-22

    Yes, now it works OK! Well done.

     

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