#1119 Broadcast SMI

[Anonymous]

Write to pci2isa register 0xb2 (APM command register) should generate SMI. This is fine and the SMI is generated in current Bochs code. But in current code SMI is delivered only to CPU(0) even in multiprocessor system which is not correct.

Write to APM command register should cause broadcast SMI so the SMI will be delivered to ALL logical processors on the system and they all will enter SMM mode. All the processors shoudl initialize SMM at the time - this is how it works in real life

I tried to make this change in acpi.cc apic_bus_broadcast_smi instead of apic_bus_deliver_smi and run it with Bochs configured SMP and 2 CPUS. But the current BIOS failed to boot when SMI is delivered to both CPUs.

Stanislav

[Nobody/Anonymous]

Logged In: NO

But the current BIOS failed to boot when SMI is delivered to both CPUs.

Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3B: System Programming Guide, Part 2
Chapter 24.12
In multiple-processor systems, initialization software must adjust the SMBASE value
for each processor so that the SMRAM state save areas for each processor do not
overlap.

I don't think this is implemented yet. A comment in rombios32start.S says
"code to relocate SMBASE to 0xa0000", so i guess if all cpus get the SMI
they all relocate to the same address.

• Sebastian