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Blowfish VHDL Core / News: Recent posts

BlowfishVHDL 2.0 Released

I got around to finishing the 2.0 work I'd started a year or so ago. Enjoy the result.


  • Completely rewritten in a more modern style.
  • Full self-checking test bench with official test vectors.
  • Easier to maintain, modify, optimize.
  • Easier to target to modern FPGAs.
Posted by Wesley J. Landaker 2007-11-08

BlowfishVHDL 1.0 Released

This was the latest version in CVS from 2004; it was a rework of the original code, and works pretty much flawlessly, but may have a few quirks in the wishbone interface. There is a v2.0 in the works in Subversion, but I'm releasing the final v1.0 because it's sooo much better than the v0.9 code.

Posted by Wesley J. Landaker 2006-06-12

Migrated to Subversion, New Version Under Development

The project is now completely hosted in Subversion instead of CVS. The working version in the trunk of CVS has been ported over. (No old history was kept, but the CVS tree is still functional.)

There are currently two versions in Subverison. In the trunk was the last rewrite I made a few years ago. It is a very good implementation, much better than any of the "released" versions. I never released this version because I didn't ever validate it in hardware.... read more

Posted by Wesley J. Landaker 2006-06-10

New version in CVS

There is now the first cut of a new version in CVS.
This version is about twice as fast as the previous version, is smaller, and better written, so it will be a great starting point for additional optimizations. The new wishbone interface is very handy for integrating in SoC type designs, but the native interface is still around for those designs where it makes more sense.

There is quite a bit of cleanup work that needs to be done, and there are a few very minor known issues that will be clean up pretty soon. Once these are done, I will make a new "official" release, but for now you'll have to track CVS for a bit if you're interested in the changes.

Posted by Wesley J. Landaker 2004-07-10

New version in the works

Due to continued interest in this project, I've decided it's time for some improvements. Since the current core is rather messy (I wrote it years ago), I've started a complete rewrite of most parts. There will also be some improvements, such as a Wishbone slave interface and a better regression test that includes all of the official test vectors.

Current status of the rewrite is about 50% done; I expect it to be finished and fully tested in just a few weeks. It's not currently availible in SF CVS; I'll check in the first version once it passes the first test vectors.

Posted by Wesley J. Landaker 2004-07-05

Minor update == minor screwup

Heh heh. Well, that minor update I made had a bug in it at the top level. Some signals were not connected correctly.

I'll get a fix uploaded in a few days, but in the meantime, you can either use the original version, or see if you can find the component that got hooked up wrong. ;)

Posted by Wesley J. Landaker 2003-07-15

Minor update

I did this project way back when I first learned VHDL. It was functional and hopefully has been useful to the many people who have downloaded it.

Since I actually have another project where this would be useful to use, I've decided to resurrect the design--probably incrementally rewrite it completely to optimize for performance (clock rate and cycle-latency).

In the mean time, I made a few quick updates to get rid of a bunch of bad stuff I had in there (synopsys proprietary packages masquerading as standard ones, for instance).... read more

Posted by Wesley J. Landaker 2003-04-30

Project Status

Well, I've verified this blowfish model on several tools and on several types of Xilinx FPGA's. Since everything is working well, and I have PLENTY of other projects to work on in the meantime, I probably won't do another release of this until one of the following happens:

  1. Somebody finds a bug and tells me about it.
  2. There is a feature that someone is dying to have.
  3. I get the motivation to go rewrite it or optimize it more.... read more
Posted by Wesley J. Landaker 2000-12-11

Verification with other CAD Tools

I have been doing some work trying to verify this design with some various CAD tools. So far, Synopsis and Synplicity work well.

I'm interested in trying some other tools, but have yet to have a chance to try it. If anyone has used this design with any other tool and has had success, I'd appreciate if you'd let me know.

Posted by Wesley J. Landaker 2000-11-11

CVS tree imported

I just imported my CVS tree--look there for up-to-date changes as they are made. =)

Posted by Wesley J. Landaker 2000-10-28

BlowfishVHDL on Xilinx Virtex

I just targeted blowfishvhdl-0.9beta1 to a Xilinx XCV1000 FPGA using Synplify and the Xilinx map/place/route tools. Everything works without a charm, and with the lowest effort level of placing and routing, the reported design speed was about 32MHz for a XCV1000-4bg560 part. It takes about 1/3 of the chip if no BlockRAMs are used. If the on chip BlockRAMs were used, it would take about 1/6th of the chip. Since the initialization arrays are static, this means you could share those arrays. If you had them share key data as well, that would reduce per-instance size as well.... read more

Posted by Wesley J. Landaker 2000-10-28

Faster than I expected

Well, I got this preliminary beta release up sooner than I expected. It's really rough, and hasn't had the code cleanup done on it that I'm going to be doing in the next few weeks, but it's full functional.

Posted by Wesley J. Landaker 2000-10-20

Coming really! =)

Since I bare openned this project, I haven't yet had a chance to set everything up and submit the current files. However, they'll be post by at least 01 Nov 2000, if not sooner. =)

Posted by Wesley J. Landaker 2000-10-20