CVS: blob/src/blob memsetup-s3c2500.S,1.1,1.2

[Russ D. <ru...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv2207

Modified Files:
	memsetup-s3c2500.S 
Log Message:
add protection unit and remap for s3c2500

Index: memsetup-s3c2500.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-s3c2500.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- memsetup-s3c2500.S	4 Sep 2003 18:03:09 -0000	1.1
+++ memsetup-s3c2500.S	27 Nov 2003 03:36:56 -0000	1.2
@@ -47,33 +47,21 @@
 .text
 .globl memsetup
 
-MEM_START:	.long	0x40000000
-
-/*
- * CFGREG : SDRAM Configuration 0 register 
- * note that ras, rc, rcd, and rp regs are *actual* values, not
- * the value + 1 
- */
-cfgreg:		.long	\
-	(RAS(6) | RC(9) | RCD(3) | RP(3) | \
-	 D1_128M | D0_128M | CL(3) | NO_AP | XW32)
-
+/* CFGREG : SDRAM Configuration 0 register */
+cfgreg:		.long	CFGREG_VAL /* defined in board header */
  
 /* CMDREG : SDRAM Configuration 1 register */
 cmdreg:		.long	(0)
 
 /* refresh rate */
-refcyc:		.long	\
-	(GET_MHz(BUS_SPEED) * 15 + ((GET_MHz(BUS_SPEED) * 6) / 10))
+refcyc:		.long	REFCYC_VAL /* defined in board header */
 
-/* Flash config, may need to be put into the board file */
-#define FLASH_SPEED 90
+/* Flash config, FLASH_SPEED is defined in the board header */
 b0con:		.long	\
 	(DW16 | BS(2) | \
 	TACC((FLASH_SPEED * GET_MHz(BUS_SPEED) + 999) / 1000) | \
 	TPA(0xE) | TACS(0) | TCOS(0) | TCOH(0))
 
-
 /* Architecture headers can customized the memory setup behavior with
  * the following defines:
  *	 
@@ -112,15 +100,16 @@
 	str	r1, [r0, #CMDREG]
 
 	/* Step 3: Write 0xF into the refresh timer register.
-	mov	r1, #0x20
+	mov	r1, #0xF
 	str	r1, [r0, #REFREG]
 
 	/* Step 4: Wait 120 clock cycles to get at least 8 refreshes */
-	mov	r4, #0x78
+	mov	r4, #120
 1:	subs	r4, r4, #1 /* more than 120 cycles */
 	bne	1b
 
-	/* Step 5: Program the normal operational value into the refresh timer */
+	/* Step 5: Program the normal operational value into the refresh 
+	 * timer */
 	ldr	r1, refcyc
 	str	r1, [r0, #REFREG]
 	
@@ -140,7 +129,7 @@
 	ldr	r1, cmdreg
 	str	r1, [r0, #CMDREG]
 
-	mov	r1, #0
+	mov	r1, #0			/* No writebuffer */
 	str	r1, [r0, #WBTOREG]
 
 	/* Setup the flash bank */
@@ -148,9 +137,76 @@
 	orr	r0, r0, #BCONB
 	ldr	r1, b0con
 	str	r1, [r0, #B0CON]
-
+	
 	mov	pc, lr
 #endif
+
+
+/* Region definitions (from board config file) */
+regions:
+.long REGION0
+.long REGION1
+.long REGION2
+.long REGION3
+.long REGION4
+.long REGION5
+.long REGION6
+.long REGION7 
+
+/* Setup the protection unit what the kernel is expecting */
+.globl protectionsetup	
+protectionsetup:
+	adr	r8, regions
+	ldmia	r8, {r0-r7}
+	mcr	p15, 0, r0, c6, c0, 0
+	mcr	p15, 0, r0, c6, c0, 1
+
+	mcr	p15, 0, r1, c6, c1, 0
+	mcr	p15, 0, r1, c6, c1, 1
+
+	mcr	p15, 0, r2, c6, c2, 0
+	mcr	p15, 0, r2, c6, c2, 1
+
+	mcr	p15, 0, r3, c6, c3, 0
+	mcr	p15, 0, r3, c6, c3, 1
+
+	mcr	p15, 0, r4, c6, c4, 0
+	mcr	p15, 0, r4, c6, c4, 1
+
+	mcr	p15, 0, r5, c6, c5, 0
+	mcr	p15, 0, r5, c6, c5, 1
+
+	mcr	p15, 0, r6, c6, c6, 0
+	mcr	p15, 0, r6, c6, c6, 1
+
+	mcr	p15, 0, r7, c6, c7, 0
+	mcr	p15, 0, r7, c6, c7, 1
+
+	mov	r0, #REGIONCACHE @ Enable appropriate caches
+	mcr	p15, 0, r0, c2, c0, 0
+	mcr	p15, 0, r0, c2, c0, 1
+
+	mov	r0, #REGIONWB	@ Enable write buffer where appropriate
+	mcr	p15, 0, r0, c3, c0, 0
+	mcr	p15, 0, r0, c3, c0, 1
+
+	mov	r0, #1<<16	@ Enable full access permission
+	subs	r0, r0, #1
+	mcr	p15, 0, r0, c5, c0, 0
+	mcr	p15, 0, r0, c5, c0, 1
+
+	/* Flush I-cache/D-cache */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0 @ I cache
+	mcr	p15, 0, r0, c6, c5, 0 @ D cache
+
+	/* Enable Caches and protection unit */
+	mrc     p15, 0, r0, c1, c0, 0
+	orr     r0, r0, #0x1000		@ I cache enabled
+	orr     r0, r0, #0x5		@ D cache/protection unit
+	mcr     p15, 0, r0, c1, c0, 0
+
+	mov	pc, lr
 
 /* -------------------------------------------------- */