CVS: blob/include/blob/arch ra_alpha.h,1.3,1.4

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory sc8-pr-cvs1:/tmp/cvs-serv9071/include/blob/arch

Modified Files:
	ra_alpha.h 
Log Message:
Fix silly typos.
Fix CCCR setting.
Add CPLD register definitions.


Index: ra_alpha.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/ra_alpha.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- ra_alpha.h	11 Nov 2003 12:40:55 -0000	1.3
+++ ra_alpha.h	11 Nov 2003 14:27:12 -0000	1.4
@@ -74,23 +74,59 @@
 #define RAMDISK_SIZE		(4 * 1024)
 
 #if 1 /* Full Speed */
-// #define MDREFR_VALUE	0x0009f018
-// #define MDCNFG_VALUE	0x000019c9
+//# define MDREFR_VALUE	0x0009f018
+//# define MDCNFG_VALUE	0x000019c9
 # define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
-						  MDCNFG_DNB0 | MDCNFG_DTC0(1) )
+						  MDCNFG_DNB0 | MDCNFG_DTC0(1) | MDCNFG_DLATCH0	| \
+						  MDCNFG_DSA1111_0 )
 # define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
-# 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
-# 						  MDREFR_K2DB2 )
+ 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
+ 						  MDREFR_K2DB2 )
 #define MDMRS_VALUE		0x00020002
-#define CCCR_VALUE		( CCCR_L(27) | CCCR_M(4) | CCCR_N(1) )
+/* L=27, M=4, N=1 */
+#define CCCR_VALUE		( CCCR_L(1) | CCCR_M(3) | CCCR_N(2) )
 #else /* SDRAM at half speed */
 # define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
 						  MDCNFG_DNB0 | MDCNFG_DTC0(1) )
 # define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
-# 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
-# 						  MDREFR_K1DB2 | MDREFR_K2DB2 )
+ 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
+ 						  MDREFR_K1DB2 | MDREFR_K2DB2 )
 # define MDMRS_VALUE	0x00020002
 #endif
+
+/*
+ * RotAlign CPLD registers
+ */
+#define RA_CPLD_BASE	(PXA_CS2_PHYS)
+#define RA_CTRL0		(RA_CPLD_BASE + 0x90)
+#define RA_CTRL1		(RA_CPLD_BASE + 0xA0)
+
+/* CTRL0 */
+#define RA_CTRL0_USBSLAVE	( 1<<0 )
+#define RA_CTRL0_X1			( 1<<1 )
+#define RA_CTRL0_X2			( 1<<2 )
+#define RA_CTRL0_nLAN_EN	( 1<<3 )
+#define RA_CTRL0_X4			( 1<<4 )
+#define RA_CTRL0_X5			( 1<<5 )
+#define RA_CTRL0_X6			( 1<<6 )
+#define RA_CTRL0_LCD_EN		( 1<<7 )
+
+
+/* CTRL 1 */
+#define RA_CTRL1_RS3_MUX(x) 	( (((u_char)x)&0x03)<<0 )
+#define RA_CTRL1_RS3_MUX0	( 1<<0 )
+#define RA_CTRL1_RS3_MUX1	( 1<<1 )
+#define RA_CTRL1_nSRST		( 1<<2 )
+#define RA_CTRL1_RS3_RS485_TERM	( 1<<3 )
+#define RA_CTRL1_BEEP		( 1<<4 )
+#define RA_CTRL1_LCD_POWER	( 1<<5 )
+#define RA_CTRL1_6		( 1<<6 )
+#define RA_CTRL1_7		( 1<<7 )
+
+/* Some shorthand macros */
+#define MEM( x )        (*((u32 *)(x)))
+#define SET(reg,bit)	((reg) |= (1<<(bit)))
+#define RST(reg,bit)	((reg) &= ~(1<<(bit)))
 
 /* GPIO configuration */
 #define GPIO0_VALUE		GPIO_OUT_LO