CVS: blob/include/blob/arch pxa-regs.h,1.2,1.3

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory sc8-pr-cvs1:/tmp/cvs-serv18268

Modified Files:
	pxa-regs.h 
Log Message:
Added MDREFR_DRI and CCCR defines.


Index: pxa-regs.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/pxa-regs.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pxa-regs.h	4 Sep 2003 01:01:15 -0000	1.2
+++ pxa-regs.h	11 Nov 2003 12:31:09 -0000	1.3
@@ -1123,6 +1123,9 @@
 #define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
 #define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
 #define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
+#define CCCR_L(x)	(((x)&0x1f) << 0 )
+#define CCCR_M(x)	(((x)&3) << 5 )
+#define CCCR_N(x)	(((x)&7) << 7 )
 
 #define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
 #define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
@@ -1352,6 +1355,7 @@
 #define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
+#define MDREFR_DRI(x)	(((x)&0xfff) << 0 )	/* SDRAM refresh interval */
 
 #define MSC_RT			Fld(2,0)	/* ROM type */
 #define MSC_NonBrst		(0 << FShft (MSC_RT))