Menu
▾
▴
CVS: blob/src/blob Makefile.am,1.39,1.40 badge4.c,1.16,1.17 chain.S,1.3,1.4 clock.c,1.3,1.4 dafit.c,1.2,1.3 hackkit.c,1.4,1.5 idr.c,1.12,1.13 initcalls.c,1.5,1.6 jornada720.c,1.7,1.8 load_kernel.c,1.15,1.16 memsetup-pxa250.S,1.1,1.2 pxa_idp.c,1.3,1.4 start-pxa.S,1.1,1.2 start-sa11x0.S,1.5,1.6 start.S,1.11,1.12 system3.c,1.28,1.29
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:55:44
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv7704/src/blob
Modified Files:
Makefile.am badge4.c chain.S clock.c dafit.c hackkit.c idr.c
initcalls.c jornada720.c load_kernel.c memsetup-pxa250.S
pxa_idp.c start-pxa.S start-sa11x0.S start.S system3.c
Log Message:
Support for CSIR IMS board and also a working PXA25x port. Still needs some
cleaning up and the lubbock and PXA IDP targets are going to be broken by
this (not sure if they ever worked and fixing them is trivial).
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.39
retrieving revision 1.40
diff -u -d -r1.39 -r1.40
--- Makefile.am 3 Apr 2003 15:02:57 -0000 1.39
+++ Makefile.am 6 Aug 2003 22:55:41 -0000 1.40
@@ -25,14 +25,13 @@
blob-rest-elf32 \
blob-rest \
blob-elf32 \
- blob \
- blob-chain-elf32 \
- blob-chain
+ blob
INCLUDES += \
-I${top_builddir}/include \
- -I${top_srcdir}/include
+ -I${top_srcdir}/include \
+ -I${LINUX_INCLUDE}
# ---- Built sources -------------------------------------------------
@@ -43,7 +42,7 @@
rest-ld-script: rest-ld-script.in
- $(CC) -x c-header -undef -nostdinc ${INCLUDES} -E $< | sed 's/^#.*//' > $@
+ $(CC) -x c-header -undef -nostdinc ${INCLUDES} -D__ASSEMBLY__ -E $< | sed 's/^#.*//' > $@
commands.c:
${top_srcdir}/src/commands/make_commands.sh @BLOB_COMMANDS@ > $@
@@ -88,7 +87,7 @@
smc9196.c \
accelent_sa.c assabet.c brutus.c badge4.c cep.c clart.c dafit.c frodo.c \
hackkit.c h3600.c idr.c jornada720.c lart.c miniprint.c nesa.c pleb.c \
- shannon.c system3.c trizeps.c pxa_idp.c
+ shannon.c system3.c trizeps.c pxa_idp.c csir_ims.c
blob_rest_elf32_DEPENDENCIES = \
@@ -154,6 +153,7 @@
memsetup-sa1100.S \
memsetup-sa1110.S \
start-pxa.S \
+ gpio-pxa.S \
start-sa11x0.S
blob_elf32_DEPENDENCIES = \
@@ -178,38 +178,6 @@
blob: blob-elf32
- $(OBJCOPY) $(OCFLAGS) $< $@
-
-
-# ---- Blob first stage chain loader --------------------------------
-
-# WARNING: chain.S *must* be the first file, otherwise the target will
-# be linked in the wrong order!
-blob_chain_elf32_SOURCES = \
- chain.S
-
-EXTRA_blob_chain_elf32_SOURCES= \
- ledasm-mmap.S \
- ledasm-sa11x0.S
-
-blob_chain_elf32_DEPENDENCIES =\
- start-ld-script \
- @BLOB_LED_STARTCODE@ \
- blob-rest-piggy.o
-
-blob_chain_elf32_LDFLAGS += \
- -Wl,-T,${srcdir}/start-ld-script \
- -Wl,-Map,blob-start-chain-elf32.map
-
-blob_chain_elf32_LDADD += \
- @BLOB_LED_STARTCODE@ \
- -lgcc
-
-
-blob_chain_SOURCES =
-
-
-blob-chain: blob-chain-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
Index: badge4.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/badge4.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- badge4.c 13 Feb 2003 01:10:53 -0000 1.16
+++ badge4.c 6 Aug 2003 22:55:41 -0000 1.17
@@ -29,7 +29,7 @@
#include <blob/arch/badge4.h>
#include <blob/flash.h>
#include <blob/init.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/reboot.h>
#include <blob/serial.h>
#include <blob/util.h>
Index: chain.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/chain.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- chain.S 10 Feb 2003 23:07:05 -0000 1.3
+++ chain.S 6 Aug 2003 22:55:41 -0000 1.4
@@ -58,7 +58,7 @@
#endif
/* init LED */
- bl ledinit
+ //bl ledinit
/* assume that the CPU and the memory are already set up at
* this point. also assume that interrupts are disabled, and if
@@ -95,7 +95,7 @@
/* turn off the LED. if it stays off it is an indication that
* we didn't make it into the C code
*/
- bl led_off
+ //bl led_off
/* blob is copied to ram, so jump to it */
Index: clock.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/clock.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- clock.c 7 Oct 2001 23:01:08 -0000 1.3
+++ clock.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -39,7 +39,7 @@
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/types.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/util.h>
Index: dafit.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/dafit.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- dafit.c 11 Apr 2003 21:24:12 -0000 1.2
+++ dafit.c 6 Aug 2003 22:55:41 -0000 1.3
@@ -46,8 +46,8 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
-#include <blob/sa1111.h>
+#include <blob/arch.h>
+#include <blob/proc/sa1111.h>
#include <blob/generic_io.h>
Index: hackkit.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/hackkit.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- hackkit.c 13 Feb 2003 01:10:53 -0000 1.4
+++ hackkit.c 6 Aug 2003 22:55:41 -0000 1.5
@@ -46,7 +46,7 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
/**********************************************************************
* defines
Index: idr.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/idr.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- idr.c 13 Feb 2003 01:10:53 -0000 1.12
+++ idr.c 6 Aug 2003 22:55:41 -0000 1.13
@@ -30,7 +30,7 @@
#include <blob/init.h>
#include <blob/reboot.h>
#include <blob/serial.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/sa1111.h>
#include <blob/led.h>
Index: initcalls.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/initcalls.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- initcalls.c 3 Apr 2003 14:58:16 -0000 1.5
+++ initcalls.c 6 Aug 2003 22:55:41 -0000 1.6
@@ -35,17 +35,11 @@
#include <blob/time.h>
#include <blob/gio_drivers.h>
-
-
-
/* default serial initialisation */
static void serial_default_init(void)
{
serial_init(TERMINAL_SPEED);
}
-
-
-
/* init calls */
__initlist(serial_default_init, INIT_LEVEL_INITIAL_HARDWARE);
Index: jornada720.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/jornada720.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- jornada720.c 13 Feb 2003 01:10:53 -0000 1.7
+++ jornada720.c 6 Aug 2003 22:55:41 -0000 1.8
@@ -28,7 +28,7 @@
#include <blob/flash.h>
#include <blob/init.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/reboot.h>
#include <blob/serial.h>
#include <blob/time.h>
Index: load_kernel.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/load_kernel.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- load_kernel.c 28 Jan 2003 04:58:26 -0000 1.15
+++ load_kernel.c 6 Aug 2003 22:55:41 -0000 1.16
@@ -110,7 +110,7 @@
}
if (!p) {
- eprintf("Unable to find kernel");
+ eprintf("Unable to find kernel\n");
return EINVAL;
}
Index: memsetup-pxa250.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-pxa250.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- memsetup-pxa250.S 14 Aug 2002 21:04:23 -0000 1.1
+++ memsetup-pxa250.S 6 Aug 2003 22:55:41 -0000 1.2
@@ -1,262 +1,225 @@
+
/*
- * Ripped from RedBoot, will add disclaimer later
+ * memory-pxa.S - Part of the AVO Architecture Boot Loader
+ *
+ * Written by Abraham van der Merwe <ab...@bl...>
+ * Copyright (c) 2002, 2003 Blio Corporation (Pty) Ltd.
+ * All Rights Reserved.
*/
#ifdef HAVE_CONFIG_H
-# include <blob/config.h>
+#include <blob/config.h>
#endif
#include <blob/arch.h>
.text
-.globl memsetup
-
-@****************************************************************************
-@ Initlialize Memory Controller
-@ The sequence below is based on the recommended init steps detailed in the
-@ PXA Processor Developers Manual section 6.12
-@
-
-memsetup:
-
- @ pause for 200 uSecs to allow internal clocks to settle
-
- ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec,
- @ so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- @ get memory controller base address
- ldr r1, =MEMC_BASE_PHYSICAL
-
-@*****************************************************************************
-@ Step 1
-@
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
+#define MDCNFG_OFFSET 0x00
+#define MDREFR_OFFSET 0x04
+#define MSC0_OFFSET 0x08
+#define MSC1_OFFSET 0x0c
+#define MSC2_OFFSET 0x10
+#define MECR_OFFSET 0x14
+#define SXLCR_OFFSET 0x18
+#define SXCNFG_OFFSET 0x1c
+#define SXMRS_OFFSET 0x24
+#define MCMEM0_OFFSET 0x28
+#define MCMEM1_OFFSET 0x2c
+#define MCATT0_OFFSET 0x30
+#define MCATT1_OFFSET 0x34
+#define MCIO0_OFFSET 0x38
+#define MCIO1_OFFSET 0x3c
+#define MDMRS_OFFSET 0x40
- @ write msc1
- ldr r2, =MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
+/*
+ * The sequence below is based on the recommended init steps detailed
+ * in the Intel PXA255 Processor Developer's Manual Section 6.11
+ */
- @ write msc2
- ldr r2, =MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
+.macro wait
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, #768
+ bls 0b
+.endm
- @ write mecr
- ldr r2, =MECR_VAL
- str r2, [r1, #MECR_OFFSET]
+/*
+ * memory_setup - Initialize Memory (SDRAM, static memory, flash, etc)
+ *
+ * INPUT: none
+ * OUTPUT: none
+ * TRASHED: r0 - r4
+ */
+.globl memsetup
+.type memsetup, #function
+memsetup:
+ /* wait for internal clocks to stabilize */
+ wait
- @ write mcmem0
- ldr r2, =MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
+ ldr r1, =0x48000000
- @ write mcmem1
- ldr r2, =MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
+ /* write MSC0, read back to ensure data latches */
+#ifdef MSC0_VALUE
+ ldr r0, =MSC0_VALUE
+ str r0, [r1, #MSC0_OFFSET]
+ ldr r0, [r1, #MSC0_OFFSET]
+#endif /* #ifdef MSC0_VALUE */
- @ write mcatt0
- ldr r2, =MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
+ /* write MSC1, read back to ensure data latches */
+#ifdef MSC1_VALUE
+ ldr r0, =MSC1_VALUE
+ str r0, [r1, #MSC1_OFFSET]
+ ldr r0, [r1, #MSC1_OFFSET]
+#endif /* #ifdef MSC1_VALUE */
- @ write mcatt1
- ldr r2, =MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
+ /* write MSC2, read back to ensure data latches */
+#ifdef MSC2_VALUE
+ ldr r0, =MSC2_VALUE
+ str r0, [r1, #MSC2_OFFSET]
+ ldr r0, [r1, #MSC2_OFFSET]
+#endif /* #ifdef MSC2_VALUE */
- @ write mcio0
- ldr r2, =MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
+ /* write MECR */
+#ifdef MECR_VALUE
+ ldr r0, =MECR_VALUE
+ str r0, [r1, #MECR_OFFSET]
+#endif /* #ifdef MECR_VALUE */
- @ write mcio1
- ldr r2, =MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
+ /* write MCMEM0 */
+#ifdef MCMEM0_VALUE
+ ldr r0, =MCMEM0_VALUE
+ str r0, [r1, #MCMEM0_OFFSET]
+#endif /* #ifdef MCMEM0_VALUE */
- @*********************************************************************
- @ Step 1, 3rd bullet
- @
+ /* write MCMEM1 */
+#ifdef MCMEM1_VALUE
+ ldr r0, =MCMEM1_VALUE
+ str r0, [r1, #MCMEM1_OFFSET]
+#endif /* #ifdef MCMEM1_VALUE */
- @ get the mdrefr settings (k0run, e0pin, etc.)
- ldr r3, =MDREFR_VAL
+ /* write MCATT0 */
+#ifdef MCATT0_VALUE
+ ldr r0, =MCATT0_VALUE
+ str r0, [r1, #MCATT0_OFFSET]
+#endif /* #ifdef MCATT0_VALUE */
- @ extract DRI field (we need a valid DRI field)
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- orr r4, r4, r3
-
- @ write back mdrefr
- str r4, [r1, #MDREFR_OFFSET]
+ /* write MCATT1 */
+#ifdef MCATT1_VALUE
+ ldr r0, =MCATT1_VALUE
+ str r0, [r1, #MCATT1_OFFSET]
+#endif /* #ifdef MCATT1_VALUE */
- @ *Note: preserve the mdrefr value in r4 *
+ /* write MCIO0 */
+#ifdef MCIO0_VALUE
+ ldr r0, =MCIO0_VALUE
+ str r0, [r1, #MCIO0_OFFSET]
+#endif /* #ifdef MCIO0_VALUE */
-@*****************************************************************************
-@ Step 2
-@ I dont know why, but this was commented out in RedBoot
-@
- @ fetch sxcnfg value
- @
- @ldr r2, =0
- @ write back sxcnfg
- @str r2, [r1, #SXCNFG_OFFSET]
+ /* write MCIO1 */
+#ifdef MCIO1_VALUE
+ ldr r0, =MCIO1_VALUE
+ str r0, [r1, #MCIO1_OFFSET]
+#endif /* #ifdef MCIO1_VALUE */
- @ if sxcnfg=0, do not program for synch-static memory
- @cmp r2, #0
- @beq 1f
+ /* get the mdrefr settings (k0run, e0pin, etc.) */
+ ldr r3, =MDREFR_VALUE
- @program sxmrs
- @ldr r2, =SXMRS_SETTINGS
- @str r2, [r1, #SXMRS_OFFSET]
+ /* extract DRI field (we need a valid DRI field) */
+ ldr r2, =0xfff
+ and r3, r3, r2
+ /* get the reset state of MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
-@*****************************************************************************
-@ Step 3
-@ I am hard-coding in 50/100/300 clock speeds for now.
-@ This needs testing since I hacked up a large, ugly version of this that was
-@ Lubbock-specific. -Rusty
-@
+ /* clear the DRI field */
+ bic r4, r4, r2
- @ Assumes previous MDREFR value in r4, if not then read current MDREFR
+ /* insert the valid DRI field loaded above */
+ orr r4, r4, r3
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free)
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K1RUN if bank 0 installed
- orr r4, r4, #0x00010000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
- @ set K1DB2 (SDClk[1] = MemClk/2)
- orreq r4, r4, #0x00020000
+ /*
+ * I am hard-coding in 50/100/300 clock speeds for now.
+ * This needs testing since I hacked up a large, ugly version
+ * of this that was Lubbock-specific. -Rusty
+ */
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
+ /* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
- @ deassert SLFRSH
- bic r4, r4, #0x00400000
-
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
+ /* set K1RUN if bank 0 installed */
+ orr r4, r4, #0x00010000
- @ assert E1PIN
- orr r4, r4, #0x00008000
-
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
+ /* set K1DB2 (SDClk[1] = MemClk/2) */
+ orreq r4, r4, #0x00020000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
-@*****************************************************************************
-@ Step 4
-@
- @ fetch platform value of MDCNFG
- ldr r2, =MDCNFG_VAL
+ /* deassert SLFRSH */
+ bic r4, r4, #0x00400000
- @ disable all sdram banks
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
- @ program banks 0/1 for bus width
- bic r2, r2, #MDCNFG_DWID0_32B @ 0=32-bit
+ /* assert E1PIN */
+ orr r4, r4, #0x00008000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
- @ write initial value of MDCNFG, w/o enabling sdram banks
- str r2, [r1, #MDCNFG_OFFSET]
+.rept 3
+ nop
+.endr
+ /* fetch platform value of MDCNFG */
+ ldr r2, =MDCNFG_VALUE
-@*****************************************************************************
-@ Step 5
-@
- @ pause for 200 uSecs
- ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec,
- @ so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
+ /* disable all sdram banks */
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-@*****************************************************************************
-@ Step 6
-@
- @ turn everything off (caches off, MMU off, etc.)
- mov r0, #0x78
- mcr p15, 0, r0, c1, c0, 0
+ /* write initial value of MDCNFG, w/o enabling sdram banks */
+ str r2, [r1, #MDCNFG_OFFSET]
+ /* wait for internal clocks to stabilize */
+ wait
-@*****************************************************************************
-@ Step 7
-@
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ CBR is generated for all banks
-
- ldr r2, =SDRAM_BASE_PHYSICAL
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
+ /* turn everything off (caches off, MMU off, etc.) */
+ mov r0, #0x78
+ mcr p15, 0, r0, c1, c0, 0
+ /*
+ * Access memory *not yet enabled* for CBR refresh cycles (8)
+ * CBR is generated for all banks
+ */
-@*****************************************************************************
-@ Step 8: NOP (enable dcache if you wanna... we dont)
-@
+ ldr r2, =PXA_SDRAM_BANK0
+.rept 8
+ str r2, [r2]
+.endr
-@*****************************************************************************
-@ Step 9
-@
- @ get memory controller base address
- ldr r1, =MEMC_BASE_PHYSICAL
+ /* fetch current MDCNFG value */
+ ldr r3, [r1, #MDCNFG_OFFSET]
- @ fetch current mdcnfg value
- ldr r3, [r1, #MDCNFG_OFFSET]
+ /* enable sdram bank 0 if installed (must do for any populated bank) */
+ orr r3, r3, #MDCNFG_DE0
- @ enable sdram bank 0 if installed (must do for any populated bank)
- orr r3, r3, #MDCNFG_DE0
+ /* write back mdcnfg, enabling the sdram bank(s) */
+ str r3, [r1, #MDCNFG_OFFSET]
- @ write back mdcnfg, enabling the sdram bank(s)
- str r3, [r1, #MDCNFG_OFFSET]
+ /* write MDMRS */
+ ldr r2, =MDMRS_VALUE
+ str r2, [r1, #MDMRS_OFFSET]
+ mov pc, lr
-@*****************************************************************************
-@ Step 10
-@
- @ write MDMRS
- ldr r2, =MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
-@*****************************************************************************
-@ Step 11: Final Step
-@ Omitted, used to contain work around for old A0 PXA250 stepping
-@
- @ return
- mov pc, lr
Index: pxa_idp.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/pxa_idp.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pxa_idp.c 13 Feb 2003 01:10:53 -0000 1.3
+++ pxa_idp.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -100,14 +100,14 @@
/* select drivers */
reboot_driver = &pxa_reboot_driver;
serial_driver = &pxa_serial_driver;
- led_driver = &sa11x0_gpio_led_driver;
+ led_driver = /*&sa11x0_gpio_led_driver*/NULL;
}
__initlist(accelent_sa_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
-
+#if 0
/*********************************************************************
* cmd_download_file
*
@@ -243,3 +243,4 @@
static char flasherasehelp[] = "ferase adr size(bytes)\n"
"erase a flash region\n";
__commandlist( cmd_flash_erase, "ferase", flasherasehelp );
+#endif
Index: start-pxa.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-pxa.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- start-pxa.S 14 Aug 2002 21:04:25 -0000 1.1
+++ start-pxa.S 6 Aug 2003 22:55:41 -0000 1.2
@@ -28,214 +28,111 @@
.text
- @ We start by implementing *all* exception vectors
+/*
+ * We start by implementing *all* exception vectors
+ *
+ * Reset vector: this initialises the machine
+ * note here that this not yet taken sleep wakeup into account -- lets just
+ * get something to work first.
+ */
- @ Reset vector: this initialises the machine
- @ note here that this not yet taken sleep wakeup into account -- lets just
- @ get something to work first.
+.macro blink, count
+ mov r3, \count
+ b endless_blink
+.endm
.globl reset
reset:
- @ First, mask **ALL** interrupts
- ldr r0, =ICMR
- mov r1, #0x00
- str r1, [r0]
+ /* First, mask **ALL** interrupts */
+ ldr r0, =ICMR
+ mov r1, #0x00
+ str r1, [r0]
real_reset:
+ bl ledsetup
+ bl memsetup
+ bl normal_boot
-#ifdef LUBBOCK
- @ Lubbock must initialize GPIO before any chip selects will work.
- bl gpio_init
-
- @ now that chip selects will work, turn on lubbock HW registers, SRAM
- @ and ethernet contoller chip selects
- ldr r3, =MSC1
- ldr r2, =MSC1_VAL
- str r2, [r3]
- ldr r2, [r3] @ need to read it back to latch it
-#endif
-
- bl ledinit
-
- @ setup memory
- bl memsetup
-
- @ loop here infinitely until I can get this to compile and boot
- @ TODO: get this to compile and boot.
-crap:
- b crap
-
- @ turn off the LED. if it stays off it is an indication that
- @ we didnt make it into the C code
- bl led_off
-
- @ everything is said and done over here, call normal_boot in
- @ the generic startup code to continue the boot procedure
- bl normal_boot
-
- @ oops, normal_boot returns, something went wrong. signal an
- @ error to the user
- mov r6, #2
- b endless_blink
-
-
-
-
-/* we could choose to handle all exceptions in a nice way, but the
- * best is to treat them as errors because blob should not contain
- * errors
- */
+ blink #1
-/* Undefined instruction exception */
.globl undefined_instruction
undefined_instruction:
- mov r6, #3
- b endless_blink
-
-
-
+ blink #2
-/* SWI */
.globl software_interrupt
software_interrupt:
- /* NOTE: This is NOT an error! If you think that blob should return
- * from software interrupts, you're plain WRONG. The source of the
- * problem is in the kernel: you should *disable* CONFIG_ANGELBOOT
- * simply because blob is not angel. -- Erik
- */
- mov r6, #4
- b endless_blink
-
-
-
+ blink #3
-/* prefetch exception. shouldn't happen though we usually run with
- * i-cache enabled */
.globl prefetch_abort
prefetch_abort:
- mov r6, #5
- b endless_blink
-
-
-
+ blink #4
-/* data abort */
.globl data_abort
data_abort:
- mov r6, #6
- b endless_blink
-
-
-
+ blink #5
-/* we *should* never reach this */
.globl not_used
not_used:
- mov r6, #7
- b endless_blink
-
-
-
+ blink #6
-/* interrupt. we could handle this differently later if some kind of
- * driver in blob wants to be interrupt driven. for the time being we
- * treat it as an error.
- */
.globl irq
irq:
- mov r6, #8
- b endless_blink
-
-
-
+ blink #7
-/* FIQ. same as IRQ */
.globl fiq
fiq:
- mov r6, #9
- b endless_blink
-
-
-
-
-/* endless loop that blinks the LED. r6 contains the number of blinks */
-endless_blink:
- bl wait
- mov r0, r6
- bl led_blink
- b endless_blink
-
-wait:
- /* busy wait loop*/
- mov r5, #0x1000000
-wait0:
- subs r5, r5, #1
- bne wait0
- mov pc, lr
-
-#ifdef LUBBOCK
-@ initialize GPIO. This should be moved to its own file eventually...
-
-init_gpio:
- ldr r0, =GPSR0
- ldr r1, =0x00008000
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =0x00FC0382
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =0x0001FFFF //0x0001C000
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =0x0060A800
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =0x00FF0382
- str r1, [r0]
+ blink #8
- ldr r0, =GPDR2
- ldr r1, =0x0001C000
- str r1, [r0]
+#define GPIO25_LED GPIO_bit(25)
- ldr r0, =GAFR0_L
- ldr r1, =0x98400000
- str r1, [r0]
+ledset:
+#ifdef CSIR_IMS
+ ldr r1, =GPSR0
+ mov r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ mov pc, lr
- ldr r0, =GAFR0_U
- ldr r1, =0x00002950
- str r1, [r0]
+ledclear:
+#ifdef CSIR_IMS
+ ldr r1, =GPCR0
+ mov r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ mov pc, lr
- ldr r0, =GAFR1_L
- ldr r1, =0x000A9558
- str r1, [r0]
+ledsetup:
+ mov r2, lr
+#ifdef CSIR_IMS
+ ldr r1, =GPDR0
+ ldr r0, [r1]
+ orr r0, r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ bl ledclear
+ mov pc, r2
- ldr r0, =GAFR1_U
- ldr r1, =0x0005AAAA
- str r1, [r0]
+.macro wait, count
+ mov r0, \count
+0:
+ subs r0, r0, #1
+ bne 0b
+.endm
- ldr r0, =GAFR2_L
- ldr r1, =0xA0000000
- str r1, [r0]
+ledflash:
+ mov r2, lr
+ bl ledset
+ wait #0x400000
+ bl ledclear
+ wait #0x400000
+ mov pc, r2
- ldr r0, =GAFR2_U
- ldr r1, =0x00000002
- str r1, [r0]
+endless_blink:
+ mov r4, r3
+0:
+ bl ledflash
+ subs r4, r4, #1
+ bne 0b
+ wait #0x2000000
+ b endless_blink
- mov pc, lr
-#endif
Index: start-sa11x0.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-sa11x0.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- start-sa11x0.S 26 Jul 2002 07:22:36 -0000 1.5
+++ start-sa11x0.S 6 Aug 2003 22:55:41 -0000 1.6
@@ -120,6 +120,9 @@
real_reset:
+ /* init GPIOs */
+ bl gpiosetup
+
/* init LED */
bl ledinit
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- start.S 10 Feb 2003 23:07:06 -0000 1.11
+++ start.S 6 Aug 2003 22:55:41 -0000 1.12
@@ -47,7 +47,8 @@
/* Jump vector table as in table 3.1 in [1] */
.globl _start
-_start: b reset
+_start:
+ b reset
b undefined_instruction
b software_interrupt
b prefetch_abort
@@ -57,29 +58,27 @@
b fiq
/* some defines to make life easier */
-/* main memory starts at 0xc0000000 */
BLOB_START: .word BLOB_ABS_BASE_ADDR
piggy_start: .word __piggy_start
piggy_end: .word __piggy_end
-
+.align
.globl normal_boot
normal_boot:
/* check the first 1MB of BLOB_START in increments of 4k */
- mov r7, #0x1000
- mov r6, r7, lsl #8 /* 4k << 2^8 = 1MB */
- ldr r5, BLOB_START
+ mov r7, #0x1000
+ mov r6, r7, lsl #8 /* 4KB << 8 = 1MB */
+ ldr r5, BLOB_START
mem_test_loop:
- mov r0, r5
- bl testram
- teq r0, #1
- beq endless_loop /* oops, something went wrong :( */
+ mov r0, r5
+ bl testram
+ teq r0, #1
+ beq endless_loop /* oops, something went wrong :( */
- add r5, r5, r7
+ add r5, r5, r7
subs r6, r6, r7
- bne mem_test_loop
-
+ bne mem_test_loop
relocate:
/* relocate the second stage loader */
@@ -102,7 +101,6 @@
cmp r0, r2
ble copy_loop
-
/* blob is copied to ram, so jump to it */
ldr r0, BLOB_START
mov pc, r0
@@ -114,3 +112,4 @@
* loop. FIXME! -- erik
*/
b endless_loop
+
Index: system3.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/system3.c,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- system3.c 3 Apr 2003 14:47:42 -0000 1.28
+++ system3.c 6 Aug 2003 22:55:41 -0000 1.29
@@ -46,7 +46,7 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/sa1111.h>
#include <blob/generic_io.h>
|
