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CVS: blob/include/blob/arch hackkit.h,NONE,1.1 Makefile.am,1.11,1.12
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From: Stefan E. <se...@us...> - 2002-11-26 18:52:57
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Update of /cvsroot/blob/blob/include/blob/arch In directory sc8-pr-cvs1:/tmp/cvs-serv31229/include/blob/arch Modified Files: Makefile.am Added Files: hackkit.h Log Message: - initial port to the Hack Kit core cpu board --- NEW FILE: hackkit.h --- /* * hackkit.h: hw defs for the hack kit. * * Copyright (C) 2001 Erik Mouw (J.A...@it...) * Copyright (C) 2002 Stefan Eletzhofer <ste...@el...> * * $Id: hackkit.h,v 1.1 2002/11/26 18:52:52 seletz Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #ident "$Id: hackkit.h,v 1.1 2002/11/26 18:52:52 seletz Exp $" #ifndef BLOB_ARCH_HKIT_H #define BLOB_ARCH_HKIT_H #define CPU_SPEED_133 //#undef CPU_SPEED_133 /* boot CPU speed */ #ifdef CPU_SPEED_133 # define CPU_SPEED (CPU_CORE_SPEED_132mhz) #else # define CPU_SPEED (CPU_CORE_SPEED_206mhz) #endif /* serial port */ #define USE_SERIAL1 #define TERMINAL_SPEED baud_115200 #define HKIT_LED_RED (0x00400000) /* GPIO 22 */ #define HKIT_LED_GRN (0x00800000) /* GPIO 23 */ /* GPIO for the LED */ #define LED_GPIO HKIT_LED_GRN /* the base address were BLOB is loaded by the first stage loader */ #define BLOB_ABS_BASE_ADDR (0xc0200400) /* where do various parts live in RAM */ #define BLOB_RAM_BASE (0xc0100000) #define KERNEL_RAM_BASE (0xC0008000) #define PARAM_RAM_BASE (0xc0110000) #define RAMDISK_RAM_BASE (0xC0400000) /* and where do they live in flash */ #define BLOB_FLASH_BASE (0x00000000) #define BLOB_FLASH_LEN (256 * 1024) #define PARAM_FLASH_BASE (0x00040000) #define PARAM_FLASH_LEN (256 * 1024) #define CONFIG_FLASH_BASE (0x00040000) #define CONFIG_FLASH_LEN (256 * 1024) #define KERNEL_FLASH_BASE (0x00080000) #define KERNEL_FLASH_LEN (1024 * 1024) #define LOAD_RAMDISK 1 /* load ramdisk into ram */ #define RAMDISK_FLASH_BASE (0x00180000) #define RAMDISK_FLASH_LEN (1536 * 1024) #define ROOTFS_FLASH_BASE (0x00300000) #define ROOTFS_FLASH_LEN (0x00600000) /* 6M */ #define DATAFS_FLASH_BASE (0x00900000) #define DATAFS_FLASH_LEN (0x00700000) /* 7M */ #define RAM_START (0xc1000000) #define RAM_SIZE (16*1024*1024) /* the position of the kernel boot parameters */ #define BOOT_PARAMS (0xc0000100) /* the size (in kbytes) to which the compressed ramdisk expands */ #define RAMDISK_SIZE (8 * 1024) /* let SDRAM run at FULL memclk speed */ #undef MDREFR_MEMCLK_FULLSPEED_0 #undef MDREFR_MEMCLK_FULLSPEED_1 #undef MDREFR_MEMCLK_FULLSPEED_2 #if 0 #define MDREFR_MEMCLK_FULLSPEED_0 #define MDREFR_MEMCLK_FULLSPEED_1 #define MDREFR_MEMCLK_FULLSPEED_2 #endif /* Memory configuration */ #ifdef BLOB_NEED_MEMCONFIG #define MSC0_VALUE_66_150 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(10) | MSC_RDN(2) | MSC_RRR(1) #define MSC0_VALUE_66_120 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 8) | MSC_RDN(2) | MSC_RRR(1) #define MSC0_VALUE_66_100 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 7) | MSC_RDN(2) | MSC_RRR(1) #define MSC1_VALUE_66 MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5) | MSC_RDN(1) | MSC_RRR(1) | ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30) | MSC_RDN(30) | MSC_RRR(7))<<16) #define MSC2_VALUE_66 MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(6) | MSC_RRR(3) #define MECR_VALUE_66 MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f) #define MSC0_VALUE_100_150 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(16) | MSC_RDN(3) | MSC_RRR(2) #define MSC0_VALUE_100_120 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2) #define MSC0_VALUE_100_100 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2) #define MSC1_VALUE_100 MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5) | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30) | MSC_RDN(30) | MSC_RRR(7))<<16) #define MSC2_VALUE_100 MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(6) | MSC_RRR(3) #define MECR_VALUE_100 MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f) /* The Hack Kit core cpu board uses: * - SDRAM: 2x Samsung K4S561632C 256Mbit (4Mx16Bitx4banks) * - Flash: * 32 bit version: 2x INTEL StrataFlash 28F128J3A */ #ifndef CPU_SPEED_133 // 206 Mhz #define MDCNFG_VALUE MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) |\ MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(2) #if 0 #define MDCNFG_VALUE MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \ MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(6) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1) #endif # define MDCAS00_VALUE 0xAAAAAA9F # define MDCAS01_VALUE 0xAAAAAAAA # define MDCAS02_VALUE 0xAAAAAAAA # define MDCAS20_VALUE 0xAAAAAA9F # define MDCAS21_VALUE 0xAAAAAAAA # define MDCAS22_VALUE 0xAAAAAAAA # define MSC0_VALUE MSC0_VALUE_100_150 # define MSC1_VALUE MSC1_VALUE_100 # define MSC2_VALUE MSC2_VALUE_100 # define MECR_VALUE MECR_VALUE_100 # define SMCNFG_VALUE 0 #else /* 133 Mhz From the intel calculator: MDCNFG = 0000000000000000 10 11 0001 0 110 1 1 11 = 0x0000B16F => DRAC=6 TRP=1 TDL=3 TRW=2 SMCNFG = 00000000000000000000000000000000 = 0x00000000 MDREFR = 0000000001110000 000000000100 0001 = 0x00700041 => TRASR=1 DRI=4 MDCAS00 = 01010101010101010101010101010111 = 0x55555557 MDCAS01 = 01010101010101010101010101010101 = 0x55555555 MDCAS02 = 01010101010101010101010101010101 = 0x55555555 MDCNFG = 0000000000000000 10 10 0001 0 110 1 1 11 = 0x0000A16F DTIM0=1 DWID0=1 DRAC=6 CDB20=1 TRP=1 TDL=2 TRW=2 SMCNFG = 00000000000000000000000000000000 = 0x00000000 MDREFR = 0000000001110000000000000100 0001 = 0x00700041 MDCAS00 = 01010101010101010101010101010111 = 0x55555557 MDCAS01 = 01010101010101010101010101010101 = 0x55555555 MDCAS02 = 01010101010101010101010101010101 = 0x55555555 */ # define MDCNFG_VALUE MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) |\ MDCNFG_TRP0(1) | MDCNFG_TDL0(2) | MDCNFG_TWR0(2) # define MDCAS00_VALUE 0x55555557 # define MDCAS01_VALUE 0x55555555 # define MDCAS02_VALUE 0x55555555 # define MDCAS20_VALUE 0xAAAAAA9F # define MDCAS21_VALUE 0xAAAAAAAA # define MDCAS22_VALUE 0xAAAAAAAA # define MSC0_VALUE MSC0_VALUE_66_150 # define MSC1_VALUE 0 # define MSC2_VALUE 0 # define MECR_VALUE 0 # define SMCNFG_VALUE 0 #endif #endif #endif Index: Makefile.am =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch/Makefile.am,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- Makefile.am 14 Oct 2002 13:17:29 -0000 1.11 +++ Makefile.am 26 Nov 2002 18:52:52 -0000 1.12 @@ -18,6 +18,7 @@ cep.h \ clart.h \ frodo.h \ + hackkit.h \ h3600.h \ idr.h \ jornada720.h \ |
