From: Abraham vd M. <ab...@2d...> - 2002-10-14 10:17:03
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Hi Russell! > > That's what I gathered. However in the SDRAM SPD (Serial Presence Detec= t - > > the little EEPROM which contains the info about the DIMM) module, the > > refresh time goes from 3.9us up to 125us which is orders of magnitude > > shorter than all the other refresh times I've seen. >=20 > 64ms / 4096 =3D ~15us Thanks. That clears it up. One more question. You're currently ignoring the burst access times when configuring MDREFR. Isn't that dangerous? (if you have any bursts, its going to take too long to refresh and then the DRAM contents will corrupt) or am I missing something? Also, the SPD datasheet refers to SDRAM burst lengths of 1, 2, 4, 8 and full page. Is that 1,2,4,8 clocks? What is a full page? Is that across all the rows? Does it need multiple clock cycles to refresh a row (i.e. cas latency * rows =3D=3D longs burst access?) --=20 Regards Abraham * netgod opens his mailbox and immediately wishes he hadnt __________________________________________________________ Abraham vd Merwe - 2d3D, Inc. Device Driver Development, Outsourcing, Embedded Systems Cell: +27 82 565 4451 Snailmail: Tel: +27 21 761 7549 Block C, Aintree Park Fax: +27 21 761 7648 Doncaster Road Email: ab...@2d... Kenilworth, 7700 Http: http://www.2d3d.com South Africa |