Re: How to configure MDREFR on StrongARM SA-1110

[Russell K. - A. L. <li...@ar...>]

On Mon, Oct 14, 2002 at 10:17:40AM +0200, Abraham vd Merwe wrote:
> In arch/arm/mach-sa1110/cpu-sa1110.c I see that Russel seems to do
> 
> (Tref >> rows) / 32
> 
> where Tref is in clocks which makes sense apart from the bug (it should be /
> rows, not >> rows) and the fact that it doesn't take burst access into
> account.

That's not a bug.  "rows" here is the number of address bits for a row
address.  In the intel documentation, they're talking about the number
of rows - in other words 2^row_bits.  So shifting right is the correct
thing to do in our case.

> The refresh time found in SDRAM SPD's - is that per row or for the whole
> module? Must be per row, since the longest possible refresh time is 125us.

Tref is the time between refreshes on a single row of dynamic RAM.  As
an example, take a Tref of 64ms and 12-bits of row address (ie, 4096
rows.)

This means that row 0 must be refreshed every 64ms.  Or to put it another
way, you need to refresh all rows in the chip within 64ms:

       0ms                       64ms
       v                         v
time:  ------------------------------------>
rownr:  0   1   2   3 ... 4095    0   1   2