CVS: blob/include/blob/proc pxa.h,NONE,1.1

[Jeff S. <je...@us...>]

Update of /cvsroot/blob/blob/include/blob/proc
In directory usw-pr-cvs1:/tmp/cvs-serv22760

Added Files:
	pxa.h 
Log Message:
Added support for PXA processors, Lubbock and PXA IDP machines


--- NEW FILE: pxa.h ---
/*
 * proc/pxa.h - processor specific defines
 * 
 * Copyright (C) 2001  Erik Mouw (J.A...@it...)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ifndef BLOB_PXA_PROC_H
#define BLOB_PXA_PROC_H

/*
 * Intel PXA internal I/O mappings:
 *
 * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
 * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
 * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
 */

#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )

#ifndef __ASSEMBLY__


# define __REG(x)	(*((volatile u32 *)io_p2v(x)))

# define __REG2(x,y)	\
	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )

# define __PREG(x)	(io_v2p((u32)&(x)))

#else

# define __REG(x)	io_p2v(x)
# define __PREG(x)	io_v2p(x)

#endif


#define __ASM_ARCH_HARDWARE_H
#include <asm-arm/arch-pxa/pxa-regs.h>

/* memory start and end */
/* are these values proc or arch specific? */
#define MEMORY_START		(0xa0000000)
#define MEMORY_END		(0xc0000000)

/**********************************************************************
 *  Memory Config Register Indices
 *  based on 0xA0000000
 */

#define MDCNFG_OFFSET    0x0
#define MDREFR_OFFSET    0x4
#define MSC0_OFFSET      0x8
#define MSC1_OFFSET      0xC
#define MSC2_OFFSET      0x10
#define MECR_OFFSET      0x14
#define SXLCR_OFFSET     0x18
#define SXCNFG_OFFSET    0x1C
#define FLYCNFG_OFFSET   0x20
#define SXMRS_OFFSET     0x24                                       
#define MCMEM0_OFFSET    0x28
#define MCMEM1_OFFSET    0x2C
#define MCATT0_OFFSET    0x30
#define MCATT1_OFFSET    0x34
#define MCIO0_OFFSET     0x38
#define MCIO1_OFFSET     0x3C
#define MDMRS_OFFSET     0x40

#define MDCNFG_DE0       (1 << 0)
#define MDCNFG_DE1       (1 << 1)
#define MDCNFG_DE2       (1 << 16)
#define MDCNFG_DE3       (1 << 17)
#define MDCNFG_DWID0_32B (0 << 3)

#endif