CVS: blob/src/blob start-sa11x0.S,1.4,1.5

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv4677

Modified Files:
	start-sa11x0.S 
Log Message:
revert to 1.3

Index: start-sa11x0.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-sa11x0.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- start-sa11x0.S	25 Jul 2002 17:25:20 -0000	1.4
+++ start-sa11x0.S	26 Jul 2002 07:22:36 -0000	1.5
@@ -44,16 +44,16 @@
 /* some defines to make life easier */
 /* Register addresses can be found in [1] Appendix A */
 IC_BASE:        .word   0x90050000
-#define _ICMR    0x04
+#define ICMR    0x04
 	
 PWR_BASE:	.word	0x90020000
-#define _PSSR	0x04
-#define _PSPR	0x08
-#define _PPCR	0x14
-#define _POSR	0x1C
+#define PSSR	0x04
+#define PSPR	0x08
+#define PPCR	0x14
+#define POSR	0x1C
 	
 RST_BASE:	.word	0x90030000
-#define _RCSR	0x04
+#define RCSR	0x04
 
 
 
@@ -76,16 +76,16 @@
 	/* First, mask **ALL** interrupts */
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
-	str	r1, [r0, #_ICMR]
+	str	r1, [r0, #ICMR]
 
 	/* switch CPU to correct speed */
 	ldr	r0, PWR_BASE
 	ldr	r1, cpuspeed
-	str	r1, [r0, #_PPCR]
+	str	r1, [r0, #PPCR]
 
 	/* check if this is a wake-up from sleep */
 	ldr	r0, RST_BASE
-	ldr	r1, [r0, #_RCSR]
+	ldr	r1, [r0, #RCSR]
 	and	r1, r1, #0x0f
 	tst	r1, #0x08	/* check the Sleep Mode Reset bit */
 	beq	real_reset	/* no, continue booting */
@@ -93,14 +93,14 @@
 	/* Wait for the oscillator to stabilize */
 	ldr	r0, PWR_BASE
 wait_for_OOK:
-	ldr	r1, [r0, #_POSR]
+	ldr	r1, [r0, #POSR]
 	tst	r1, #1		/* test Oscillator OK bit */
 	beq	wait_for_OOK
 
 	/* yes, a wake-up. clear RCSR by writing a 1 (see 9.6.2.1 from [1]) */
 	ldr	r0, RST_BASE
 	mov	r1, #0x08
-	str	r1, [r0, #_RCSR]	;
+	str	r1, [r0, #RCSR]	;
 
 	/* setup memory */
 	bl	memsetup
@@ -108,14 +108,14 @@
 	/* handle Power Manager Sleep Status Register (PSSR)
 	 * see 9.5.7.5 from [1]*/
 	ldr	r0, PWR_BASE
-	ldr r1, [r0, #_PSSR]
+	ldr r1, [r0, #PSSR]
 	/* clear PH bit, bring periperal pins out from sleep state */
 	orr r1, r1, #0x10
-	str r1, [r0, #_PSSR]
+	str r1, [r0, #PSSR]
 	
 	/* get the value from the PSPR and jump to it */
 	ldr	r0, PWR_BASE
-	ldr	r1, [r0, #_PSPR]
+	ldr	r1, [r0, #PSPR]
 	mov	pc, r1