CVS: blob/include/blob sa1111.h,1.5,1.6

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Update of /cvsroot/blob/blob/include/blob
In directory usw-pr-cvs1:/tmp/cvs-serv32431

Modified Files:
	sa1111.h 
Log Message:
- dont include the kernel headers anymore. They changed during 2.4.xx and
  now they changed in 2.5.xx again. Let's have our own header (created from
  the kernel header, w/o the physical/virtual address access macros).


Index: sa1111.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/sa1111.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6

--- sa1111.h	11 Feb 2002 16:54:23 -0000	1.5
+++ sa1111.h	29 Apr 2002 09:37:11 -0000	1.6
@@ -1,5 +1,6 @@
 /*
- * sa1111.h: wrapper file to include asm/arch-sa1100/SA-1111.h
+ * sa1111.h: Defines and macros for accessing the SA1111. Created from
+ * the kernel source.
  *
  * Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
  *
@@ -28,18 +29,529 @@
 
 #include <blob/arch.h>
 
-#ifndef SA1111_BASE
-# error "Define SA1111_BASE address in architecture specific include file"
-#endif
+#define SA1111_VBASE	0x40000000
+
+/*
+ * 26 bits of the SA-1110 address bus are available to the SA-1111.
+ * Use these when feeding target addresses to the DMA engines.
+ */
+#define MEM_REG(adr)	(*((u32 *)(adr)))
+
+#define SA1111_ADDR_WIDTH	(26)
+#define SA1111_ADDR_MASK	((1<<SA1111_ADDR_WIDTH)-1)
+#define SA1111_DMA_ADDR(x)	((x)&SA1111_ADDR_MASK)
+
+/*
+ * Don't ask the (SAC) DMA engines to move less than this amount.
+ */
+
+#define SA1111_SAC_DMA_MIN_XFER	(0x800)
+
+/*
+ * SA1111 register definitions.
+ */
+#define SA1111_REG(x)	MEM_REG(SA1111_VBASE + (x))
+
+/* System Bus Interface (SBI)
+ *
+ * Registers
+ *    SKCR	Control Register
+ *    SMCR	Shared Memory Controller Register
+ *    SKID	ID Register
+ */
+#define SA1111_SKCR	0x0000
+#define SA1111_SMCR	0x0004
+#define SA1111_SKID	0x0008
+
+#define SBI_SKCR	SA1111_REG(SA1111_SKCR)
+#define SBI_SMCR	SA1111_REG(SA1111_SMCR)
+#define SBI_SKID	SA1111_REG(SA1111_SKID)
+
+#define SKCR_PLL_BYPASS	(1<<0)
+#define SKCR_RCLKEN	(1<<1)
+#define SKCR_SLEEP	(1<<2)
+#define SKCR_DOZE	(1<<3)
+#define SKCR_VCO_OFF	(1<<4)
+#define SKCR_SCANTSTEN	(1<<5)
+#define SKCR_CLKTSTEN	(1<<6)
+#define SKCR_RDYEN	(1<<7)
+#define SKCR_SELAC	(1<<8)
+#define SKCR_OPPC	(1<<9)
+#define SKCR_PLLTSTEN	(1<<10)
+#define SKCR_USBIOTSTEN	(1<<11)
+/*
+ * Don't believe the specs!  Take them, throw them outside.  Leave them
+ * there for a week.  Spit on them.  Walk on them.  Stamp on them.
+ * Pour gasoline over them and finally burn them.  Now think about coding.
+ *  - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
+ *  - The Feb 2001 errata (278260-010) says that the previous errata
+ *    (278260-009) is wrong, and its bit actually 12, fixed in spec
+ *    278242-003.
+ *  - The SA1111 manual (278242) says bit 12, but 0 to enable.
+ *  - Reality is bit 13, 1 to enable.
+ *      -- rmk
+ */
+#define SKCR_OE_EN	(1<<13)
+
+#define SMCR_DTIM	(1<<0)
+#define SMCR_MBGE	(1<<1)
+#define SMCR_DRAC_0	(1<<2)
+#define SMCR_DRAC_1	(1<<3)
+#define SMCR_DRAC_2	(1<<4)
+#define SMCR_DRAC	Fld(3, 2)
+#define SMCR_CLAT	(1<<5)
+
+#define SKID_SIREV_MASK	(0x000000f0)
+#define SKID_MTREV_MASK (0x0000000f)
+#define SKID_ID_MASK	(0xffffff00)
+#define SKID_SA1111_ID	(0x690cc200)
+
+/*
+ * System Controller
+ *
+ * Registers
+ *    SKPCR	Power Control Register
+ *    SKCDR	Clock Divider Register
+ *    SKAUD	Audio Clock Divider Register
+ *    SKPMC	PS/2 Mouse Clock Divider Register
+ *    SKPTC	PS/2 Track Pad Clock Divider Register
+ *    SKPEN0	PWM0 Enable Register
+ *    SKPWM0	PWM0 Clock Register
+ *    SKPEN1	PWM1 Enable Register
+ *    SKPWM1	PWM1 Clock Register
+ */
+
+#define SKPCR		SA1111_REG(0x0200)
+#define SKCDR		SA1111_REG(0x0204)
+#define SKAUD		SA1111_REG(0x0208)
+#define SKPMC		SA1111_REG(0x020c)
+#define SKPTC		SA1111_REG(0x0210)
+#define SKPEN0		SA1111_REG(0x0214)
+#define SKPWM0		SA1111_REG(0x0218)
+#define SKPEN1		SA1111_REG(0x021c)
+#define SKPWM1		SA1111_REG(0x0220)
+
+#define SKPCR_UCLKEN	(1<<0)
+#define SKPCR_ACCLKEN	(1<<1)
+#define SKPCR_I2SCLKEN	(1<<2)
+#define SKPCR_L3CLKEN	(1<<3)
+#define SKPCR_SCLKEN	(1<<4)
+#define SKPCR_PMCLKEN	(1<<5)
+#define SKPCR_PTCLKEN	(1<<6)
+#define SKPCR_DCLKEN	(1<<7)
+#define SKPCR_PWMCLKEN	(1<<8)
+
+/*
+ * USB Host controller
+ */
+
+#define USB_OHCI_OP_BASE	SA1111_REG(0x0400)
+#define USB_STATUS		SA1111_REG(0x0518)
+#define USB_RESET		SA1111_REG(0x051c)
+#define USB_INTERRUPTEST	SA1111_REG(0x0520)
+
+#define USB_RESET_FORCEIFRESET	(1 << 0)
+#define USB_RESET_FORCEHCRESET	(1 << 1)
+#define USB_RESET_CLKGENRESET	(1 << 2)
+#define USB_RESET_SIMSCALEDOWN	(1 << 3)
+#define USB_RESET_USBINTTEST	(1 << 4)
+#define USB_RESET_SLEEPSTBYEN	(1 << 5)
+#define USB_RESET_PWRSENSELOW	(1 << 6)
+#define USB_RESET_PWRCTRLLOW	(1 << 7)
+
+/*
+ * Serial Audio Controller
+ *
+ * Registers
+ *    SACR0             Serial Audio Common Control Register
+ *    SACR1             Serial Audio Alternate Mode (I2C/MSB) Control Register
+ *    SACR2             Serial Audio AC-link Control Register
+ *    SASR0             Serial Audio I2S/MSB Interface & FIFO Status Register
+ *    SASR1             Serial Audio AC-link Interface & FIFO Status Register
+ *    SASCR             Serial Audio Status Clear Register
+ *    L3_CAR            L3 Control Bus Address Register
+ *    L3_CDR            L3 Control Bus Data Register
+ *    ACCAR             AC-link Command Address Register
+ *    ACCDR             AC-link Command Data Register
+ *    ACSAR             AC-link Status Address Register
+ *    ACSDR             AC-link Status Data Register
+ *    SADTCS            Serial Audio DMA Transmit Control/Status Register
+ *    SADTSA            Serial Audio DMA Transmit Buffer Start Address A
+ *    SADTCA            Serial Audio DMA Transmit Buffer Count Register A
+ *    SADTSB            Serial Audio DMA Transmit Buffer Start Address B
+ *    SADTCB            Serial Audio DMA Transmit Buffer Count Register B
+ *    SADRCS            Serial Audio DMA Receive Control/Status Register
+ *    SADRSA            Serial Audio DMA Receive Buffer Start Address A
+ *    SADRCA            Serial Audio DMA Receive Buffer Count Register A
+ *    SADRSB            Serial Audio DMA Receive Buffer Start Address B
+ *    SADRCB            Serial Audio DMA Receive Buffer Count Register B
+ *    SAITR             Serial Audio Interrupt Test Register
+ *    SADR              Serial Audio Data Register (16 x 32-bit)
+ */
+
+#define SACR0		SA1111_REG(0x0600)
+#define SACR1		SA1111_REG(0x0604)
+#define SACR2		SA1111_REG(0x0608)
+#define SASR0		SA1111_REG(0x060c)
+#define SASR1		SA1111_REG(0x0610)
+#define SASCR		SA1111_REG(0x0618)
+#define L3_CAR		SA1111_REG(0x061c)
+#define L3_CDR		SA1111_REG(0x0620)
+#define ACCAR		SA1111_REG(0x0624)
+#define ACCDR		SA1111_REG(0x0628)
+#define ACSAR		SA1111_REG(0x062c)
+#define ACSDR		SA1111_REG(0x0630)
+#define SADTCS		SA1111_REG(0x0634)
+#define SADTSA		SA1111_REG(0x0638)
+#define SADTCA		SA1111_REG(0x063c)
+#define SADTSB		SA1111_REG(0x0640)
+#define SADTCB		SA1111_REG(0x0644)
+#define SADRCS		SA1111_REG(0x0648)
+#define SADRSA		SA1111_REG(0x064c)
+#define SADRCA		SA1111_REG(0x0650)
+#define SADRSB		SA1111_REG(0x0654)
+#define SADRCB		SA1111_REG(0x0658)
+#define SAITR		SA1111_REG(0x065c)
+#define SADR		SA1111_REG(0x0680)
+
+#define SACR0_ENB	(1<<0)
+#define SACR0_BCKD	(1<<2)
+#define SACR0_RST	(1<<3)
+
+#define SACR1_AMSL	(1<<0)
+#define SACR1_L3EN	(1<<1)
+#define SACR1_L3MB	(1<<2)
+#define SACR1_DREC	(1<<3)
+#define SACR1_DRPL	(1<<4)
+#define SACR1_ENLBF	(1<<5)
+
+#define SACR2_TS3V	(1<<0)
+#define SACR2_TS4V	(1<<1)
+#define SACR2_WKUP	(1<<2)
+#define SACR2_DREC	(1<<3)
+#define SACR2_DRPL	(1<<4)
+#define SACR2_ENLBF	(1<<5)
+#define SACR2_RESET	(1<<6)
+
+#define SASR0_TNF	(1<<0)
+#define SASR0_RNE	(1<<1)
+#define SASR0_BSY	(1<<2)
+#define SASR0_TFS	(1<<3)
+#define SASR0_RFS	(1<<4)
+#define SASR0_TUR	(1<<5)
+#define SASR0_ROR	(1<<6)
+#define SASR0_L3WD	(1<<16)
+#define SASR0_L3RD	(1<<17)
+
+#define SASR1_TNF	(1<<0)
+#define SASR1_RNE	(1<<1)
+#define SASR1_BSY	(1<<2)
+#define SASR1_TFS	(1<<3)
+#define SASR1_RFS	(1<<4)
+#define SASR1_TUR	(1<<5)
+#define SASR1_ROR	(1<<6)
+#define SASR1_CADT	(1<<16)
+#define SASR1_SADR	(1<<17)
+#define SASR1_RSTO	(1<<18)
+#define SASR1_CLPM	(1<<19)
+#define SASR1_CRDY	(1<<20)
+#define SASR1_RS3V	(1<<21)
+#define SASR1_RS4V	(1<<22)
+
+#define SASCR_TUR	(1<<5)
+#define SASCR_ROR	(1<<6)
+#define SASCR_DTS	(1<<16)
+#define SASCR_RDD	(1<<17)
+#define SASCR_STO	(1<<18)
+
+#define SADTCS_TDEN	(1<<0)
+#define SADTCS_TDIE	(1<<1)
+#define SADTCS_TDBDA	(1<<3)
+#define SADTCS_TDSTA	(1<<4)
+#define SADTCS_TDBDB	(1<<5)
+#define SADTCS_TDSTB	(1<<6)
+#define SADTCS_TBIU	(1<<7)
+
+#define SADRCS_RDEN	(1<<0)
+#define SADRCS_RDIE	(1<<1)
+#define SADRCS_RDBDA	(1<<3)
+#define SADRCS_RDSTA	(1<<4)
+#define SADRCS_RDBDB	(1<<5)
+#define SADRCS_RDSTB	(1<<6)
+#define SADRCS_RBIU	(1<<7)
+
+#define SAD_CS_DEN	(1<<0)
+#define SAD_CS_DIE	(1<<1)	/* Not functional on metal 1 */
+#define SAD_CS_DBDA	(1<<3)	/* Not functional on metal 1 */
+#define SAD_CS_DSTA	(1<<4)
+#define SAD_CS_DBDB	(1<<5)	/* Not functional on metal 1 */
+#define SAD_CS_DSTB	(1<<6)
+#define SAD_CS_BIU	(1<<7)	/* Not functional on metal 1 */
+
+#define SAITR_TFS	(1<<0)
+#define SAITR_RFS	(1<<1)
+#define SAITR_TUR	(1<<2)
+#define SAITR_ROR	(1<<3)
+#define SAITR_CADT	(1<<4)
+#define SAITR_SADR	(1<<5)
+#define SAITR_RSTO	(1<<6)
+#define SAITR_TDBDA	(1<<8)
+#define SAITR_TDBDB	(1<<9)
+#define SAITR_RDBDA	(1<<10)
+#define SAITR_RDBDB	(1<<11)
+
+/*
+ * General-Purpose I/O Interface
+ *
+ * Registers
+ *    PA_DDR		GPIO Block A Data Direction
+ *    PA_DRR/PA_DWR	GPIO Block A Data Value Register (read/write)
+ *    PA_SDR		GPIO Block A Sleep Direction
+ *    PA_SSR		GPIO Block A Sleep State
+ *    PB_DDR		GPIO Block B Data Direction
+ *    PB_DRR/PB_DWR	GPIO Block B Data Value Register (read/write)
+ *    PB_SDR		GPIO Block B Sleep Direction
+ *    PB_SSR		GPIO Block B Sleep State
+ *    PC_DDR		GPIO Block C Data Direction
+ *    PC_DRR/PC_DWR	GPIO Block C Data Value Register (read/write)
+ *    PC_SDR		GPIO Block C Sleep Direction
+ *    PC_SSR		GPIO Block C Sleep State
+ */
+
+#define PA_DDR		SA1111_REG(0x1000)
+#define PA_DRR		SA1111_REG(0x1004)
+#define PA_DWR		SA1111_REG(0x1004)
+#define PA_SDR		SA1111_REG(0x1008)
+#define PA_SSR		SA1111_REG(0x100c)
+#define PB_DDR		SA1111_REG(0x1010)
+#define PB_DRR		SA1111_REG(0x1014)
+#define PB_DWR		SA1111_REG(0x1014)
+#define PB_SDR		SA1111_REG(0x1018)
+#define PB_SSR		SA1111_REG(0x101c)
+#define PC_DDR		SA1111_REG(0x1020)
+#define PC_DRR		SA1111_REG(0x1024)
+#define PC_DWR		SA1111_REG(0x1024)
+#define PC_SDR		SA1111_REG(0x1028)
+#define PC_SSR		SA1111_REG(0x102c)
+
+/*
+ * Interrupt Controller
+ *
+ * Registers
+ *    INTTEST0		Test register 0
+ *    INTTEST1		Test register 1
+ *    INTEN0		Interrupt Enable register 0
+ *    INTEN1		Interrupt Enable register 1
+ *    INTPOL0		Interrupt Polarity selection 0
+ *    INTPOL1		Interrupt Polarity selection 1
+ *    INTTSTSEL		Interrupt source selection
+ *    INTSTATCLR0	Interrupt Status/Clear 0
+ *    INTSTATCLR1	Interrupt Status/Clear 1
+ *    INTSET0		Interrupt source set 0
+ *    INTSET1		Interrupt source set 1
+ *    WAKE_EN0		Wake-up source enable 0
+ *    WAKE_EN1		Wake-up source enable 1
+ *    WAKE_POL0		Wake-up polarity selection 0
+ *    WAKE_POL1		Wake-up polarity selection 1
+ */
+
+#define SA1111_INTTEST0		0x1600
+#define SA1111_INTTEST1		0x1604
+#define SA1111_INTEN0		0x1608
+#define SA1111_INTEN1		0x160c
+#define SA1111_INTPOL0		0x1610
+#define SA1111_INTPOL1		0x1614
+#define SA1111_INTTSTSEL	0x1618
+#define SA1111_INTSTATCLR0	0x161c
+#define SA1111_INTSTATCLR1	0x1620
+#define SA1111_INTSET0		0x1624
+#define SA1111_INTSET1		0x1628
+#define SA1111_WAKE_EN0		0x162c
+#define SA1111_WAKE_EN1		0x1630
+#define SA1111_WAKE_POL0	0x1634
+#define SA1111_WAKE_POL1	0x1638
+
+#define INTTEST0	SA1111_REG(SA1111_INTTEST0)
+#define INTTEST1	SA1111_REG(SA1111_INTTEST1)
+#define INTEN0		SA1111_REG(SA1111_INTEN0)
+#define INTEN1		SA1111_REG(SA1111_INTEN1)
+#define INTPOL0		SA1111_REG(SA1111_INTPOL0)
+#define INTPOL1		SA1111_REG(SA1111_INTPOL1)
+#define INTTSTSEL	SA1111_REG(SA1111_INTTSTSEL)
+#define INTSTATCLR0	SA1111_REG(SA1111_INTSTATCLR0)
+#define INTSTATCLR1	SA1111_REG(SA1111_INTSTATCLR1)
+#define INTSET0		SA1111_REG(SA1111_INTSET0)
+#define INTSET1		SA1111_REG(SA1111_INTSET1)
+#define WAKE_EN0	SA1111_REG(SA1111_WAKE_EN0)
+#define WAKE_EN1	SA1111_REG(SA1111_WAKE_EN1)
+#define WAKE_POL0	SA1111_REG(SA1111_WAKE_POL0)
+#define WAKE_POL1	SA1111_REG(SA1111_WAKE_POL1)
+
+/*
+ * PS/2 Trackpad and Mouse Interfaces
+ *
+ * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
+ *    KBDCR     Control Register
+ *    KBDSTAT       Status Register
+ *    KBDDATA       Transmit/Receive Data register
+ *    KBDCLKDIV     Clock Division Register
+ *    KBDPRECNT     Clock Precount Register
+ *    KBDTEST1      Test register 1
+ *    KBDTEST2      Test register 2
+ *    KBDTEST3      Test register 3
+ *    KBDTEST4      Test register 4
+ *    MSECR
+ *    MSESTAT
+ *    MSEDATA
+ *    MSECLKDIV
+ *    MSEPRECNT
+ *    MSETEST1
+ *    MSETEST2
+ *    MSETEST3
+ *    MSETEST4
+ *
+ */
+
+#define KBDCR		SA1111_REG(0x0a00)
+#define KBDSTAT		SA1111_REG(0x0a04)
+#define KBDDATA		SA1111_REG(0x0a08)
+#define KBDCLKDIV	SA1111_REG(0x0a0c)
+#define KBDPRECNT	SA1111_REG(0x0a10)
+#define MSECR		SA1111_REG(0x0c00)
+#define MSESTAT		SA1111_REG(0x0c04)
+#define MSEDATA		SA1111_REG(0x0c08)
+#define MSECLKDIV	SA1111_REG(0x0c0c)
+#define MSEPRECNT	SA1111_REG(0x0c10)
+
+#define KBDCR_ENA        0x08
+#define KBDCR_FKD        0x02
+#define KBDCR_FKC        0x01
+
+#define KBDSTAT_TXE      0x80
+#define KBDSTAT_TXB      0x40
+#define KBDSTAT_RXF      0x20
+#define KBDSTAT_RXB      0x10
+#define KBDSTAT_ENA      0x08
+#define KBDSTAT_RXP      0x04
+#define KBDSTAT_KBD      0x02
+#define KBDSTAT_KBC      0x01
+
+#define KBDCLKDIV_DivVal     Fld(4,0)
+
+#define MSECR_ENA        0x08
+#define MSECR_FKD        0x02
+#define MSECR_FKC        0x01
+
+#define MSESTAT_TXE      0x80
+#define MSESTAT_TXB      0x40
+#define MSESTAT_RXF      0x20
+#define MSESTAT_RXB      0x10
+#define MSESTAT_ENA      0x08
+#define MSESTAT_RXP      0x04
+#define MSESTAT_MSD      0x02
+#define MSESTAT_MSC      0x01
+
+#define MSECLKDIV_DivVal     Fld(4,0)
+
+#define KBDTEST1_CD      0x80
+#define KBDTEST1_RC1         0x40
+#define KBDTEST1_MC      0x20
+#define KBDTEST1_C       Fld(2,3)
+#define KBDTEST1_T2      0x40
+#define KBDTEST1_T1      0x20
+#define KBDTEST1_T0      0x10
+#define KBDTEST2_TICBnRES    0x08
+#define KBDTEST2_RKC         0x04
+#define KBDTEST2_RKD         0x02
+#define KBDTEST2_SEL         0x01
+#define KBDTEST3_ms_16       0x80
+#define KBDTEST3_us_64       0x40
+#define KBDTEST3_us_16       0x20
+#define KBDTEST3_DIV8        0x10
+#define KBDTEST3_DIn         0x08
+#define KBDTEST3_CIn         0x04
+#define KBDTEST3_KD      0x02
+#define KBDTEST3_KC      0x01
+#define KBDTEST4_BC12        0x80
+#define KBDTEST4_BC11        0x40
+#define KBDTEST4_TRES        0x20
+#define KBDTEST4_CLKOE       0x10
+#define KBDTEST4_CRES        0x08
+#define KBDTEST4_RXB         0x04
+#define KBDTEST4_TXB         0x02
+#define KBDTEST4_SRX         0x01
+
+#define MSETEST1_CD      0x80
+#define MSETEST1_RC1         0x40
+#define MSETEST1_MC      0x20
+#define MSETEST1_C       Fld(2,3)
+#define MSETEST1_T2      0x40
+#define MSETEST1_T1      0x20
+#define MSETEST1_T0      0x10
+#define MSETEST2_TICBnRES    0x08
+#define MSETEST2_RKC         0x04
+#define MSETEST2_RKD         0x02
+#define MSETEST2_SEL         0x01
+#define MSETEST3_ms_16       0x80
+#define MSETEST3_us_64       0x40
+#define MSETEST3_us_16       0x20
+#define MSETEST3_DIV8        0x10
+#define MSETEST3_DIn         0x08
+#define MSETEST3_CIn         0x04
+#define MSETEST3_KD      0x02
+#define MSETEST3_KC      0x01
+#define MSETEST4_BC12        0x80
+#define MSETEST4_BC11        0x40
+#define MSETEST4_TRES        0x20
+#define MSETEST4_CLKOE       0x10
+#define MSETEST4_CRES        0x08
+#define MSETEST4_RXB         0x04
+#define MSETEST4_TXB         0x02
+#define MSETEST4_SRX         0x01
+
+/*
+ * PCMCIA Interface
+ *
+ * Registers
+ *    PCSR	Status Register
+ *    PCCR	Control Register
+ *    PCSSR	Sleep State Register
+ */
+
 
-#define SA1111_p2v(x) (x)
-#define SA1101_p2v(PhAdd)  (PhAdd)
-#define io_p2v(x) (x)
-#define __REG(x)      (*((volatile u32 *)io_p2v(x)))
-#define __REGP(x)      (*((volatile u32 *)io_p2v(x)))
 
-/* Tell SA-1111.h to shut up; we're including it anyway. Nyah nyah ;-) */
-#define __ASM_ARCH_HARDWARE_H
-#include <asm-arm/arch-sa1100/SA-1111.h>
+
+
+#define PCCR		SA1111_REG(0x1800)
+#define PCSSR		SA1111_REG(0x1804)
+#define PCSR		SA1111_REG(0x1808)
+
+#define PCSR_S0_READY	(1<<0)
+#define PCSR_S1_READY	(1<<1)
+#define PCSR_S0_DETECT	(1<<2)
+#define PCSR_S1_DETECT	(1<<3)
+#define PCSR_S0_VS1	(1<<4)
+#define PCSR_S0_VS2	(1<<5)
+#define PCSR_S1_VS1	(1<<6)
+#define PCSR_S1_VS2	(1<<7)
+#define PCSR_S0_WP	(1<<8)
+#define PCSR_S1_WP	(1<<9)
+#define PCSR_S0_BVD1	(1<<10)
+#define PCSR_S0_BVD2	(1<<11)
+#define PCSR_S1_BVD1	(1<<12)
+#define PCSR_S1_BVD2	(1<<13)
+
+#define PCCR_S0_RST	(1<<0)
+#define PCCR_S1_RST	(1<<1)
+#define PCCR_S0_FLT	(1<<2)
+#define PCCR_S1_FLT	(1<<3)
+#define PCCR_S0_PWAITEN	(1<<4)
+#define PCCR_S1_PWAITEN	(1<<5)
+#define PCCR_S0_PSE	(1<<6)
+#define PCCR_S1_PSE	(1<<7)
+
+#define PCSSR_S0_SLEEP	(1<<0)
+#define PCSSR_S1_SLEEP	(1<<1)
 
 #endif
+



