CVS: blob/include/blob/arch system3.h,1.14,1.15

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv29173

Modified Files:
	system3.h 
Log Message:



Index: system3.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/system3.h,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- system3.h	27 Feb 2002 18:41:48 -0000	1.14
+++ system3.h	23 Apr 2002 12:25:16 -0000	1.15
@@ -26,16 +26,18 @@
 #ifndef BLOB_ARCH_SYSTEM3_H
 #define BLOB_ARCH_SYSTEM3_H
 
+//#define	CPU_SPEED_133
 #undef	CPU_SPEED_133
 
+/* SYSTEM3 with 64 MB SDRAM, all on bank0 */
+#define CONFIG_SYSTEM3_REV0802
+
 /* boot CPU speed */
 #ifdef CPU_SPEED_133
-#	define CPU_SPEED		(0x05)
+#	define CPU_SPEED		(CPU_CORE_SPEED_132mhz)
 #else
-/* 206 MHz */
-//#	define CPU_SPEED		(0x0a)
 /* 191 MHz */
-#	define CPU_SPEED		(0x09)
+#	define CPU_SPEED		(CPU_CORE_SPEED_221mhz)
 #endif
 
 /* serial port */
@@ -83,19 +85,26 @@
 #define MSC0_VALUE_66_120	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 8) | MSC_RDN(2) | MSC_RRR(1)
 #define MSC0_VALUE_66_100	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 7) | MSC_RDN(2) | MSC_RRR(1)
 #define MSC1_VALUE_66		MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1) | ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
-#define MSC2_VALUE_66		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(7)  | MSC_RDN(2) | MSC_RRR(1)
+#define MSC2_VALUE_66		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13)  | MSC_RDN(6) | MSC_RRR(3)
 #define MECR_VALUE_66		MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f)
 
 #define MSC0_VALUE_100_150	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(16) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC0_VALUE_100_120	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC0_VALUE_100_100	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC1_VALUE_100		MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
-#define MSC2_VALUE_100		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9)  | MSC_RDN(2) | MSC_RRR(1)
+//#define MSC2_VALUE_100	MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9)  | MSC_RDN(2) | MSC_RRR(1)
+#define MSC2_VALUE_100		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13)  | MSC_RDN(6) | MSC_RRR(3)
 #define MECR_VALUE_100		MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f)
 
 #ifndef CPU_SPEED_133
 //	206 Mhz
-#	define MDCNFG_VALUE	0x72547254
+#if defined(CONFIG_SYSTEM3_REV0802)
+#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
+						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(6) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
+#else
+#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
+						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(5) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
+#endif
 #	define MDCAS00_VALUE	0xAAAAAA9F
 #	define MDCAS01_VALUE	0xAAAAAAAA
 #	define MDCAS02_VALUE	0xAAAAAAAA
@@ -109,7 +118,13 @@
 #	define SMCNFG_VALUE	0
 #else
 //	133 Mhz
-#	define MDCNFG_VALUE	0x72547254
+#if defined(CONFIG_SYSTEM3_REV0802)
+#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
+						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(6) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
+#else
+#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
+						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(5) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
+#endif
 #	define MDCAS00_VALUE	0xAAAAAA9F
 #	define MDCAS01_VALUE	0xAAAAAAAA
 #	define MDCAS02_VALUE	0xAAAAAAAA
@@ -137,5 +152,10 @@
 
 #define	SA1111_BASE		(0x40000000)
 #define	SA1111_VBASE	(0x40000000)
+
+#define SYSTEM3_CTRL_0		(0x10000090)
+#define SYSTEM3_CTRL_1		(0x100000A0)
+#define SYSTEM3_CTRL_2		(0x100000B0)
+#define SYSTEM3_CTRL_IRR	(0x10000024)
 
 #endif