CVS: blob/include/blob/arch system3.h,1.9,1.10

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv7834

Modified Files:
	system3.h 
Log Message:
- standard clock rate set to 191MHz
- dont set MECR_FAST0 and MECR_FAST1


Index: system3.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/system3.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- system3.h	7 Jan 2002 16:31:25 -0000	1.9
+++ system3.h	21 Feb 2002 14:23:48 -0000	1.10
@@ -32,7 +32,10 @@
 #ifdef CPU_SPEED_133
 #	define CPU_SPEED		(0x05)
 #else
-#	define CPU_SPEED		(0x0a)
+/* 206 MHz */
+//#	define CPU_SPEED		(0x0a)
+/* 191 MHz */
+#	define CPU_SPEED		(0x09)
 #endif
 
 /* serial port */
@@ -79,13 +82,13 @@
 #define MSC0_VALUE_66_100     MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 7) | MSC_RDN(2) | MSC_RRR(1)
 #define MSC1_VALUE_66         MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1) | ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
 #define MSC2_VALUE_66         MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(7)  | MSC_RDN(2) | MSC_RRR(1)
-#define MECR_VALUE_66         0xFFFFFFFF
+#define MECR_VALUE_66         0x7FFF7FFF
 #define MSC0_VALUE_100_150    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(16) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC0_VALUE_100_120    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC0_VALUE_100_100    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC1_VALUE_100        MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
 #define MSC2_VALUE_100        MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9)  | MSC_RDN(2) | MSC_RRR(1)
-#define MECR_VALUE_100        0xFFFFFFFF
+#define MECR_VALUE_100        0x7FFF7FFF
 
 #ifndef CPU_SPEED_133
 //	206 Mhz