From: Stefan E. <se...@us...> - 2001-11-05 09:25:33
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Update of /cvsroot/blob/blob/src/diag In directory usw-pr-cvs1:/tmp/cvs-serv12083 Modified Files: system3.c Log Message: - added register display command (will fork off to a separate file later) - added smc 91c96 testing function (first shot) - cleaned up code a bit, mostly cosmetic Index: system3.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/system3.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- system3.c 2001/10/15 15:04:25 1.3 +++ system3.c 2001/11/05 09:25:31 1.4 @@ -50,10 +50,6 @@ #define SET(reg,bit) ((reg) |= (1<<(bit))) #define CLR(reg,bit) ((reg) &= ~(1<<(bit))) -#define mem_b(adr) ( ((volatile unsigned char*)0)[adr] ) -#define mem_w(adr) ( ((volatile unsigned short int*)0)[(adr)/2] ) -#define mem_dw(adr) ( ((volatile unsigned long*)(0)) [(adr)/4] ) - /* Optimization barrier */ /* The "volatile" is due to gcc bugs */ #define barrier() __asm__ __volatile__("": : :"memory") @@ -66,12 +62,36 @@ #define CPLD_2 (CPLD_BASE + 0xB0) /********************************************************************** + * types + */ +typedef struct _reg { + char *name; + u32 adr; +} register_t; + +/********************************************************************** * program globals */ /********************************************************************** * module globals */ +static register_t registers[] = { + { "MDCNFG ", 0xa0000000 + 0x0 }, + { "MDCAS00", 0xa0000000 + 0x04 }, + { "MDCAS01", 0xa0000000 + 0x08 }, + { "MDCAS02", 0xa0000000 + 0x0c }, + { "MCS0 ", 0xa0000000 + 0x10 }, + { "MCS1 ", 0xa0000000 + 0x14 }, + { "MECR ", 0xa0000000 + 0x18 }, + { "MDREFR ", 0xa0000000 + 0x1C }, + { "MDCAS20", 0xa0000000 + 0x20 }, + { "MDCAS21", 0xa0000000 + 0x24 }, + { "MDCAS22", 0xa0000000 + 0x28 }, + { "MCS2 ", 0xa0000000 + 0x2C }, + { "SMCNFG ", 0xa0000000 + 0x30 }, + { NULL, 0 } +}; /********************************************************************** * prototypes @@ -181,18 +201,90 @@ * static functions */ -static int cpldtest( int argc, char *argv[] ) +#if 0 +#define SMC_BASE 0x18000000 +#define BANK_SELECT 14 +#define LAN91C96_ECOR 0x0 +#define LAN91C96_ECSR 0x2 + +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x02 +#define ECOR_ENABLE 0x01 + +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 +#define SMC_inb( r ) (*((volatile u8 *)(base+((r)<<2)))) +static inline unsigned short __SMC_inw(unsigned base, int r) +{ + unsigned char b1, b2; + msleep(1); + b1 = SMC_inb(r); + msleep(1); + b2 = SMC_inb(r+1); + return (b2 << 8) | b1; +} +#define SMC_inw(r) __SMC_inw(base, r) +#define SMC_outb( d, r ) (*((volatile u8 *)(base+((r)<<2))) = (u8)(d)) +#define SMC_outw( d, r ) do { \ + msleep(1);\ + SMC_outb((d), r); \ + msleep(1);\ + SMC_outb((d)>>8, (r)+1);} while (0) +static int smctest( int argc, char *argv[] ) { + u32 *base = (u32 *)SMC_BASE; + u32 *attr; + u16 bank; - int i = 100000; - unsigned char x = 0; + attr = (u32 *)(((u32)base | (1<<25)) + (0x8000*4)); -label: - x = (*((unsigned char *)0x10000090)); - barrier(); - (*((unsigned char *)0x10000090)) = x; - barrier(); - goto label; + /* enable the device */ + attr[LAN91C96_ECOR] |= ECOR_RESET; + msleep(100); + + /* the device will ignore all writes to the enable bit while reset is + * asserted, even if the reset bit is cleared in the same write. Must + * clear reset first, then enable the device. + */ + attr[LAN91C96_ECOR] &= ~ECOR_RESET; + attr[LAN91C96_ECOR] |= ECOR_ENABLE; + + /* force byte mode */ + attr[LAN91C96_ECSR] |= ECSR_IOIS8; + + bank = SMC_inw( BANK_SELECT ); + SerialOutputString( "bank " ); + SerialOutputHex( bank & 0xffff ); + SerialOutputString( "\n" ); + + SMC_outw( 0, BANK_SELECT ); + bank = SMC_inw( BANK_SELECT ); + SerialOutputString( "bank " ); + SerialOutputHex( bank & 0xffff ); + SerialOutputString( "\n" ); + + return 0; } -static char cpldhelp[] = "does not return!\n"; -__commandlist(cpldtest, "cpldtest", cpldhelp); +static char smctesthelp[] = "test smc 91c96 ethernet chip\n"; +__commandlist(smctest, "smctest", smctesthelp); +#endif + +static int regs_show( int argc, char *argv[] ) +{ + int i = 0; + + i = 0; + while ( registers[i].name ) { + SerialOutputString( registers[i].name ); + SerialOutputString( "= 0x" ); + SerialOutputHex( MEM( registers[i].adr ) ); + SerialOutputByte( '\n' ); + i++; + } + + return 0; +} +static char regshelp[] = "print register info\n"; +__commandlist(regs_show, "regs", regshelp); |