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CVS: blob/src/blob lart.c,1.1,1.2 clart.c,1.1,1.2 assabet.c,1.1,1.2
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From: Erik M. <er...@us...> - 2001-10-15 21:54:20
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Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv20208
Modified Files:
lart.c clart.c assabet.c
Log Message:
Machine specific flash functions. These three are either tested (LART), or
otherwise I'm pretty sure they work (Assabet, CreditLART).
Index: lart.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/lart.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- lart.c 2001/10/14 22:36:11 1.1
+++ lart.c 2001/10/15 21:54:17 1.2
@@ -26,4 +26,115 @@
#endif
#include <blob/arch.h>
+#include <blob/errno.h>
+#include <blob/flash.h>
+#include <blob/util.h>
+
+
+
+
+/* flash descriptor for LART flash */
+/* 2x Intel 28F160F3B fast boot block flash (4MB) */
+flash_descriptor_t flash_descriptors[] =
+{
+ {
+ size: 2 * 8 * 1024,
+ num: 2,
+ lockable: 1
+ },
+ {
+ size: 2 * 8 * 1024,
+ num: 6,
+ },
+ {
+ size: 2 * 64 * 1024,
+ num: 31,
+ },
+ {
+ /* NULL block */
+ },
+};
+
+
+
+
+/* flash commands for two 16 bit intel flash chips */
+#define READ_ARRAY 0x00FF00FF
+#define ERASE_SETUP 0x00200020
+#define ERASE_CONFIRM 0x00D000D0
+#define PGM_SETUP 0x00400040
+#define STATUS_READ 0x00700070
+#define STATUS_CLEAR 0x00500050
+#define STATUS_BUSY 0x00800080
+#define STATUS_ERASE_ERR 0x00200020
+#define STATUS_PGM_ERR 0x00100010
+
+
+
+
+/* the next two functions should work for all Intel flashes */
+
+/* erases a flash block at the given address */
+int erase_flash(u32 *addr)
+{
+ u32 result;
+
+ /* prepare for erase */
+ *addr = data_to_flash(ERASE_SETUP);
+ barrier();
+ /* erase block */
+ *addr = data_to_flash(ERASE_CONFIRM);
+ barrier();
+
+ /* status check */
+ do {
+ *addr = data_to_flash(STATUS_READ);
+ barrier();
+ result = data_from_flash(*addr);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *addr = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if((result & STATUS_ERASE_ERR) != 0)
+ return -EFLASHERASE;
+
+ return 0;
+}
+
+
+
+/* write a flash block at a given location */
+int write_flash(u32 *dst, const u32* src)
+{
+ u32 result;
+
+ /* setup flash for writing */
+ *dst = data_to_flash(PGM_SETUP);
+ barrier();
+
+ /* write data */
+ *dst = *src;
+ barrier();
+
+ /* status check */
+ do {
+ *dst = data_to_flash(STATUS_READ);
+ barrier();
+
+ result = data_from_flash(*dst);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *dst = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if(((result & STATUS_PGM_ERR) != 0) || (*dst != *src))
+ return -EFLASHPGM;
+
+ return 0;
+}
Index: clart.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/clart.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- clart.c 2001/10/14 22:36:11 1.1
+++ clart.c 2001/10/15 21:54:17 1.2
@@ -26,4 +26,108 @@
#endif
#include <blob/arch.h>
+#include <blob/errno.h>
+#include <blob/flash.h>
+#include <blob/util.h>
+
+
+
+
+/* flash descriptor for CreditLART flash */
+/* 1x Intel 28F256J3A strataflash (16MB) */
+flash_descriptor_t flash_descriptors[] =
+{
+ {
+ size: 128 * 1024,
+ num: 128,
+ lockable: 1
+ },
+ {
+ /* NULL block */
+ },
+};
+
+
+
+
+/* flash commands for a single 16 bit intel flash chip */
+#define READ_ARRAY 0x000000FF
+#define ERASE_SETUP 0x00000020
+#define ERASE_CONFIRM 0x000000D0
+#define PGM_SETUP 0x00000040
+#define STATUS_READ 0x00000070
+#define STATUS_CLEAR 0x00000050
+#define STATUS_BUSY 0x00000080
+#define STATUS_ERASE_ERR 0x00000020
+#define STATUS_PGM_ERR 0x00000010
+
+
+
+
+/* the next two functions should work for all Intel flashes */
+
+/* erases a flash block at the given address */
+int erase_flash(u32 *addr)
+{
+ u32 result;
+
+ /* prepare for erase */
+ *addr = data_to_flash(ERASE_SETUP);
+ barrier();
+
+ /* erase block */
+ *addr = data_to_flash(ERASE_CONFIRM);
+ barrier();
+ /* status check */
+ do {
+ *addr = data_to_flash(STATUS_READ);
+ barrier();
+ result = data_from_flash(*addr);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *addr = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if((result & STATUS_ERASE_ERR) != 0)
+ return -EFLASHERASE;
+
+ return 0;
+}
+
+
+
+
+/* write a flash block at a given location */
+int write_flash(u32 *dst, const u32* src)
+{
+ u32 result;
+
+ /* setup flash for writing */
+ *dst = data_to_flash(PGM_SETUP);
+ barrier();
+
+ /* write data */
+ *dst = *src;
+ barrier();
+
+ /* status check */
+ do {
+ *dst = data_to_flash(STATUS_READ);
+ barrier();
+
+ result = data_from_flash(*dst);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *dst = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if(((result & STATUS_PGM_ERR) != 0) || (*dst != *src))
+ return -EFLASHPGM;
+
+ return 0;
+}
Index: assabet.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/assabet.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- assabet.c 2001/10/14 22:36:11 1.1
+++ assabet.c 2001/10/15 21:54:17 1.2
@@ -26,4 +26,102 @@
#endif
#include <blob/arch.h>
+#include <blob/errno.h>
+#include <blob/flash.h>
+#include <blob/util.h>
+
+
+/* flash descriptor for Assabet flash */
+/* 2x Intel 28F128J3A strataflash (16MB) */
+flash_descriptor_t flash_descriptors[] =
+{
+ {
+ size: 2 * 128 * 1024,
+ num: 64,
+ lockable: 1
+ },
+ {
+ /* NULL block */
+ },
+};
+
+
+
+
+/* flash commands for two 16 bit intel flash chips */
+#define READ_ARRAY 0x00FF00FF
+#define ERASE_SETUP 0x00200020
+#define ERASE_CONFIRM 0x00D000D0
+#define PGM_SETUP 0x00400040
+#define STATUS_READ 0x00700070
+#define STATUS_CLEAR 0x00500050
+#define STATUS_BUSY 0x00800080
+#define STATUS_ERASE_ERR 0x00200020
+#define STATUS_PGM_ERR 0x00100010
+
+
+
+
+int erase_flash(u32 *addr)
+{
+ u32 result;
+
+ /* prepare for erase */
+ *addr = data_to_flash(ERASE_SETUP);
+ barrier();
+
+ /* erase block */
+ *addr = data_to_flash(ERASE_CONFIRM);
+ barrier();
+
+ /* status check */
+ do {
+ *addr = data_to_flash(STATUS_READ);
+ barrier();
+ result = data_from_flash(*addr);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *addr = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if((result & STATUS_ERASE_ERR) != 0)
+ return -EFLASHERASE;
+ return 0;
+}
+
+
+
+
+int write_flash(u32 *dst, const u32* src)
+{
+ u32 result;
+
+ /* setup flash for writing */
+ *dst = data_to_flash(PGM_SETUP);
+ barrier();
+
+ /* write data */
+ *dst = *src;
+ barrier();
+
+ /* status check */
+ do {
+ *dst = data_to_flash(STATUS_READ);
+ barrier();
+
+ result = data_from_flash(*dst);
+ barrier();
+ } while((~result & STATUS_BUSY) != 0);
+
+ /* put flash back into Read Array mode */
+ *dst = data_to_flash(READ_ARRAY);
+ barrier();
+
+ if(((result & STATUS_PGM_ERR) != 0) || (*dst != *src))
+ return -EFLASHPGM;
+
+ return 0;
+}
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