blob/include memsetup.h,1.1,1.2

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include
In directory usw-pr-cvs1:/tmp/cvs-serv15960

Modified Files:
	memsetup.h 
Log Message:
- provides some defines and macros for memory config registers


Index: memsetup.h
===================================================================
RCS file: /cvsroot/blob/blob/include/memsetup.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- memsetup.h	2001/10/04 11:45:50	1.1
+++ memsetup.h	2001/10/04 11:50:54	1.2
@@ -0,0 +1,69 @@
+/*
+ * memsetup.h: include file for memory setup
+ *
+ * $Id$
+ *
+ * Copyright (C) 2001 Stefan Eletzhofer
+ *						<ste...@ww...>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ *     Developer's Manual", April 1999
+ */
+
+#ident "$Id$"
+
+/**********************************************************************
+ *  Memory Config Register Indices
+ *  based on 0xA0000000
+ */
+#define	MDCNFG	0x0
+#define MDCAS00	0x04
+#define MDCAS01	0x08
+#define MDCAS02	0x0c
+#define MCS0	0x10
+#define MCS1	0x14
+#define	MECR	0x18
+#define MDREFR	0x1C
+#define MDCAS20	0x20
+#define MDCAS21	0x24
+#define MDCAS22	0x28
+#define MCS2	0x2C
+#define	SMCNFG	0x30
+
+/**********************************************************************
+ *  MDCNFG masks
+ */
+
+/**********************************************************************
+ *  MDREFR masks
+ */
+#define MDREFR_TRASR(X)		(X & (0x0000000f))
+#define MDREFR_DRI(X)		((X & (0x00000fff)) << 4 )
+#define MDREFR_E0PIN		(1 << 16)
+#define MDREFR_K0RUN		(1 << 17)
+#define MDREFR_K0DB2		(1 << 18)
+#define MDREFR_E1PIN		(1 << 20)
+#define MDREFR_K1RUN		(1 << 21)
+#define MDREFR_K1DB2		(1 << 22)
+#define MDREFR_K2RUN		(1 << 25)
+#define MDREFR_K2DB2		(1 << 26)
+#define MDREFR_EAPD			(1 << 28)
+#define MDREFR_KAPD			(1 << 29)
+#define MDREFR_SLFRSH		(1 << 31)