From: Erik M. <er...@us...> - 2001-07-16 21:43:23
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Update of /cvsroot/blob/blob/src In directory usw-pr-cvs1:/tmp/cvs-serv12400 Modified Files: Tag: blob_1_0_9_hack start.S Log Message: - Set clock speed in a slightly more modular way - Resume-from-suspend should work right now. not yet tested with linux, but at least blob boots properly Index: start.S =================================================================== RCS file: /cvsroot/blob/blob/src/start.S,v retrieving revision 1.1.1.1.2.6 retrieving revision 1.1.1.1.2.7 diff -u -r1.1.1.1.2.6 -r1.1.1.1.2.7 --- start.S 2001/07/12 16:25:45 1.1.1.1.2.6 +++ start.S 2001/07/16 21:43:20 1.1.1.1.2.7 @@ -60,17 +60,30 @@ /* Register addresses can be found in [1] Appendix A */ IC_BASE: .word 0x90050000 #define ICMR 0x04 + PWR_BASE: .word 0x90020000 #define PSPR 0x08 #define PPCR 0x14 + RST_BASE: .word 0x90030000 #define RCSR 0x04 + +/* main memory starts at 0xc0000000 */ +MEM_START: .long 0xc0000000 -MEM_START: .word 0xc0000000 +/* The initial CPU speed. Note that the SA11x0 CPUs can be safely overclocked: + * 190 MHz CPUs are able to run at 221 MHz, 133 MHz CPUs can do 206 Mhz. + */ +#if defined SHANNON +cpuspeed: .long 0xa0 /* 206 MHz */ +#else +cpuspeed: .long 0x0b /* 221 MHz */ +#endif + /* the actual reset code */ reset: /* First, mask **ALL** interrupts */ @@ -78,20 +91,10 @@ mov r1, #0x00 str r1, [r0, #ICMR] -#if defined SHANNON - /* Switch the CPU to 206.4 MHz by writing the PPCR. */ - /* Don't worry, 206.4 MHz is also safe for 133 MHz CPUs. */ - mov r1, #0x90000000 - add r1, r1, #0x20000 - mov r2, #0x0a - str r2, [r1, #0x14] -#else - /* Switch the CPU to 221 MHz by writing the PPCR. */ - /* Don't worry, 221 MHz is also safe for 190 MHz CPUs. */ + /* switch CPU to correct speed */ ldr r0, PWR_BASE - mov r1, #0x0b + LDR r1, cpuspeed str r1, [r0, #PPCR] -#endif /* setup memory */ bl memsetup @@ -99,27 +102,28 @@ /* init LED */ bl ledinit + /* check if this is a wake-up from sleep */ + ldr r0, RST_BASE + ldr r1, [r0, #RCSR] + and r1, r1, #0x0f + teq r1, #0x08 + bne normal_boot /* no, continue booting */ + + /* yes, a wake-up. clear RCSR by writing a 1 (see 9.6.2.1 from [1]) */ + mov r1, #0x08 + str r1, [r0, #RCSR] ; + + /* get the value from the PSPR and jump to it */ + ldr r0, PWR_BASE + ldr r1, [r0, #PSPR] + mov pc, r1 + +normal_boot: /* enable I-cache */ mrc p15, 0, r1, c1, c0, 0 @ read control reg orr r1, r1, #0x1000 @ set Icache mcr p15, 0, r1, c1, c0, 0 @ write it back -/*wook found that normal_boot is never reached when this code present! */ - /* check if this is a wake-up from sleep */ -// ldr r0, RST_BASE -// ldr r1, [r0, #RCSR] -// tst r1, #0x08 -// bne normal_boot /* no, continue booting */ - - /* yes, a wake-up. get the value from the PSPR and jump to it */ -// ldr r0, PWR_BASE -// ldr r1, [r0, #PSPR] -// mov pc, r1 - - - - -normal_boot: /* check the first 1MB in increments of 4k */ mov r7, #0x1000 mov r6, r7, lsl #8 /* 4k << 2^8 = 1MB */ |