Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv10611
Modified Files:
amd32.c
Log Message:
cleanup of amd32 so that it will work for different flash bases
Index: amd32.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/amd32.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- amd32.c 19 Jun 2002 04:41:49 -0000 1.6
+++ amd32.c 27 Nov 2003 08:09:44 -0000 1.7
@@ -59,12 +59,13 @@
#define ERR 4
-static void flash_read_array_amd32(void)
+inline void flash_cmd_amd32(u32 offset, u16 cmd)
{
- *(u32 *)FLASH_ADDR1 = data_to_flash(READ_ARRAY);
+ *((u32 *)(flash_base | offset)) = data_to_flash(cmd);
barrier();
}
+
/* NOT! for amd16.c, this examines one chip of the two chip interleave */
static int get_status_amd16(u32 result, u32 last, int chip)
{
@@ -113,18 +114,13 @@
static int flash_erase_amd32(u32 *addr)
{
/* prepare for erase */
- *(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
- barrier();
- *(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
- barrier();
- *(u32 *)FLASH_ADDR1 = data_to_flash(ERASE_SETUP);
- barrier();
+ flash_cmd_amd32(FLASH_ADDR1, UNLOCK1);
+ flash_cmd_amd32(FLASH_ADDR2, UNLOCK2);
+ flash_cmd_amd32(FLASH_ADDR1, ERASE_SETUP);
/* erase command */
- *(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
- barrier();
- *(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
- barrier();
+ flash_cmd_amd32(FLASH_ADDR1, UNLOCK1);
+ flash_cmd_amd32(FLASH_ADDR2, UNLOCK2);
*addr = data_to_flash(ERASE_CONFIRM);
/* I just can't find clean ways of dealing with this flash...
@@ -144,7 +140,7 @@
if (get_status_amd32(addr) < 0) {
/* put flash back into Read Array mode */
- flash_read_array_amd32();
+ flash_cmd_amd32(FLASH_ADDR1, READ_ARRAY);
return -EFLASHERASE;
}
@@ -157,19 +153,16 @@
static int flash_write_amd32(u32 *dst, const u32* src)
{
- *(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
- barrier();
- *(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
- barrier();
- *(u32 *)FLASH_ADDR1 = data_to_flash(PGM_SETUP);
- barrier();
+ flash_cmd_amd32(FLASH_ADDR1, UNLOCK1);
+ flash_cmd_amd32(FLASH_ADDR2, UNLOCK2);
+ flash_cmd_amd32(FLASH_ADDR1, PGM_SETUP);
*dst = *src;
barrier();
if (get_status_amd32(dst) < 0 || *dst != *src) {
barrier();
- flash_read_array_amd32();
+ flash_cmd_amd32(FLASH_ADDR1, READ_ARRAY);
return -EFLASHPGM;
}
@@ -200,15 +193,12 @@
static int flash_query_block_lock_amd32(u32 *blockStart)
{
int result;
- *(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
- barrier();
- *(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
- barrier();
- *(u32 *)FLASH_ADDR1 = data_to_flash(CONFIG_QUERY);
- barrier();
+ flash_cmd_amd32(FLASH_ADDR1, UNLOCK1);
+ flash_cmd_amd32(FLASH_ADDR2, UNLOCK2);
+ flash_cmd_amd32(FLASH_ADDR1, CONFIG_QUERY);
result = *(u32 *)(blockStart + 2);
- flash_read_array_amd32();
+ flash_cmd_amd32(FLASH_ADDR1, READ_ARRAY);
return !!result;
}
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