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blob-cvs-commit
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From: Jeff S. <je...@us...> - 2002-08-14 21:04:32
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Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv24974
Modified Files:
Makefile.am main.c param_block.c start.S
Added Files:
lubbock.c memsetup-pxa250.S pxa_idp.c start-pxa.S
Log Message:
Added support for PXA processors, Lubbock and PXA IDP machines
--- NEW FILE: lubbock.c ---
/*
* lubbock.c: Lubbock specific stuff
*
* Copyright (C) 2002 Intel Corporation
* Written by Rusty Geldmacher (rus...@in...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/serial.h>
/* flash descriptor for Assabet flash */
/* 2x Intel 28F128J3A strataflash (16MB) */
static const flash_descriptor_t assabet_flash_descriptors[] =
{
{
size: 2 * 128 * 1024,
num: 64,
lockable: 1
},
{
/* NULL block */
},
};
static void init_assabet_flash_driver(void)
{
flash_descriptors = assabet_flash_descriptors;
flash_driver = &intel32_flash_driver;
}
__initlist(init_assabet_flash_driver, INIT_LEVEL_DRIVER_SELECTION);
#define RS232_ENABLE 0x00001000
#define GREEN_LED_ENABLE 0x00004000
static void assabet_init_hardware(void)
{
u32 *bcr = (u32 *)0x12000000;
/* enable RS232 tranceiver and green LED */
*bcr = RS232_ENABLE | GREEN_LED_ENABLE;
/* select serial driver */
serial_driver = &sa11x0_serial_driver;
}
__initlist(assabet_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
--- NEW FILE: memsetup-pxa250.S ---
/*
* Ripped from RedBoot, will add disclaimer later
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
.globl memsetup
@****************************************************************************
@ Initlialize Memory Controller
@ The sequence below is based on the recommended init steps detailed in the
@ PXA Processor Developers Manual section 6.12
@
memsetup:
@ pause for 200 uSecs to allow internal clocks to settle
ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 @ really 0x2E1 is about 200usec,
@ so 0x300 should be plenty
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
@ get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
@*****************************************************************************
@ Step 1
@
@ write msc0, read back to ensure data latches
@
ldr r2, =MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET]
@ write msc1
ldr r2, =MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
@ write msc2
ldr r2, =MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
@ write mecr
ldr r2, =MECR_VAL
str r2, [r1, #MECR_OFFSET]
@ write mcmem0
ldr r2, =MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
@ write mcmem1
ldr r2, =MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
@ write mcatt0
ldr r2, =MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
@ write mcatt1
ldr r2, =MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
@ write mcio0
ldr r2, =MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
@ write mcio1
ldr r2, =MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
@*********************************************************************
@ Step 1, 3rd bullet
@
@ get the mdrefr settings (k0run, e0pin, etc.)
ldr r3, =MDREFR_VAL
@ extract DRI field (we need a valid DRI field)
ldr r2, =0xFFF
@ valid DRI field in r3
and r3, r3, r2
@ get the reset state of MDREFR
ldr r4, [r1, #MDREFR_OFFSET]
@ clear the DRI field
bic r4, r4, r2
@ insert the valid DRI field loaded above
orr r4, r4, r3
@ write back mdrefr
str r4, [r1, #MDREFR_OFFSET]
@ *Note: preserve the mdrefr value in r4 *
@*****************************************************************************
@ Step 2
@ I dont know why, but this was commented out in RedBoot
@
@ fetch sxcnfg value
@
@ldr r2, =0
@ write back sxcnfg
@str r2, [r1, #SXCNFG_OFFSET]
@ if sxcnfg=0, do not program for synch-static memory
@cmp r2, #0
@beq 1f
@program sxmrs
@ldr r2, =SXMRS_SETTINGS
@str r2, [r1, #SXMRS_OFFSET]
@*****************************************************************************
@ Step 3
@ I am hard-coding in 50/100/300 clock speeds for now.
@ This needs testing since I hacked up a large, ugly version of this that was
@ Lubbock-specific. -Rusty
@
@ Assumes previous MDREFR value in r4, if not then read current MDREFR
@ clear the free-running clock bits
@ (clear K0Free, K1Free, K2Free)
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
@ set K1RUN if bank 0 installed
orr r4, r4, #0x00010000
@ set K1DB2 (SDClk[1] = MemClk/2)
orreq r4, r4, #0x00020000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
@ deassert SLFRSH
bic r4, r4, #0x00400000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
@ assert E1PIN
orr r4, r4, #0x00008000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
nop
nop
@*****************************************************************************
@ Step 4
@
@ fetch platform value of MDCNFG
ldr r2, =MDCNFG_VAL
@ disable all sdram banks
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
@ program banks 0/1 for bus width
bic r2, r2, #MDCNFG_DWID0_32B @ 0=32-bit
@ write initial value of MDCNFG, w/o enabling sdram banks
str r2, [r1, #MDCNFG_OFFSET]
@*****************************************************************************
@ Step 5
@
@ pause for 200 uSecs
ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 @ really 0x2E1 is about 200usec,
@ so 0x300 should be plenty
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
@*****************************************************************************
@ Step 6
@
@ turn everything off (caches off, MMU off, etc.)
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0
@*****************************************************************************
@ Step 7
@
@ Access memory *not yet enabled* for CBR refresh cycles (8)
@ CBR is generated for all banks
ldr r2, =SDRAM_BASE_PHYSICAL
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
@*****************************************************************************
@ Step 8: NOP (enable dcache if you wanna... we dont)
@
@*****************************************************************************
@ Step 9
@
@ get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
@ fetch current mdcnfg value
ldr r3, [r1, #MDCNFG_OFFSET]
@ enable sdram bank 0 if installed (must do for any populated bank)
orr r3, r3, #MDCNFG_DE0
@ write back mdcnfg, enabling the sdram bank(s)
str r3, [r1, #MDCNFG_OFFSET]
@*****************************************************************************
@ Step 10
@
@ write MDMRS
ldr r2, =MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
@*****************************************************************************
@ Step 11: Final Step
@ Omitted, used to contain work around for old A0 PXA250 stepping
@
@ return
mov pc, lr
--- NEW FILE: pxa_idp.c ---
/*
* accelent_sa.c: Accelent IDP specific stuff
*
* Copyright (C) 2001 Erik Mouw (J.A...@it...)
* Copyright (C) 2001 Stefan Eletzhofer
* (ste...@ww...)
* Copyright (C) 2002 Jeff Sutherland <je...@ac...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/**********************************************************************
* includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/main.h>
#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/util.h>
#include <blob/serial.h>
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/command.h>
#include <blob/uucodec.h>
#include <blob/serial.h>
extern blob_status_t blob_status;
/* flash descriptor for Accelent IDP flash. */
/* Accelent PXA IDP uses 2xINTEL e28F128 Chips */
static const flash_descriptor_t accelent_sa_flash_descriptors[] =
{
{
size: 2 * 128 * 1024,
num: 128,
lockable: 1
},
{
/* NULL block */
},
};
static int accelent_sa_flash_enable_vpp(void)
{
//TODO
//set GPIO17
return 0;
}
static int accelent_sa_flash_disable_vpp(void)
{
//TODO
//reset GPIO17
return 0;
}
static void init_accelent_sa_flash_driver(void)
{
flash_descriptors = accelent_sa_flash_descriptors;
flash_driver = &intel32_flash_driver;
flash_driver->enable_vpp = accelent_sa_flash_enable_vpp;
flash_driver->disable_vpp = accelent_sa_flash_disable_vpp;
}
__initlist(init_accelent_sa_flash_driver, INIT_LEVEL_DRIVER_SELECTION);
static void accelent_sa_init_hardware(void)
{
/* select serial driver */
serial_driver = &pxa_serial_driver;
}
__initlist(accelent_sa_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
/*********************************************************************
* cmd_download_file
*
* AUTOR: SELETZ
* REVISED:
*
* Download a file to arbitary memory location
*
*/
int cmd_download_file( int argc, char *argv[] )
{
int ret = 0;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 3 ) return -EINVAL;
ret = strtou32( argv[1], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &len );
if ( ret < 0 ) return -EINVAL;
if (blob_status.terminalSpeed != blob_status.downloadSpeed) {
SerialOutputString("Switching to download speed\n");
SerialOutputString("You have 60 seconds to switch your terminal emulator to the same speed and\n");
SerialOutputString("start downloading. After that " PACKAGE " will switch back to term speed.\n");
serial_init(blob_status.downloadSpeed);
} else {
SerialOutputString("You have 60 seconds to start downloading.\n");
}
ret = UUDecode((char *)dest, len);
if ( ret == len ) {
SerialOutputString("Received ");
SerialOutputDec(ret);
SerialOutputString(" (0x");
SerialOutputHex(ret);
SerialOutputString(") bytes.\n");
ret = 0;
} else {
SerialOutputString("error during uudecode\n");
}
if (blob_status.terminalSpeed != blob_status.downloadSpeed) {
SerialOutputString("\n(Please switch your terminal emulator back to terminal speed\n");
serial_init(blob_status.terminalSpeed);
}
return ret;
}
static char downloadhelp[] = "dlfile destadr filelength\n"
"download file to memory\n";
__commandlist( cmd_download_file, "dlfile", downloadhelp );
/*********************************************************************
* cmd_flash_write
*
* AUTOR: SELETZ
* REVISED:
*
* Command wrapper for low-level flash write access
*
*/
static int cmd_flash_write( int argc, char *argv[] )
{
int ret = 0;
u32 src = 0L;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 4 ) return -EINVAL;
ret = strtou32( argv[1], &src );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[3], &len );
if ( ret < 0 ) return -EINVAL;
if ( len & (0x3) ) {
len = (len>>2) + 1;
} else {
len = len>>2;
}
_DBGU32( src );
_DBGU32( dest );
_DBGU32( len );
ret = flash_write_region( (u32 *)dest, (u32*)src, len );
return ret;
}
static char flashwritehelp[] = "fwrite srcadr destadr size(bytes)\n"
"flash a memory region\n";
__commandlist( cmd_flash_write, "fwrite", flashwritehelp );
/*********************************************************************
* cmd_flash_erase
*
* AUTOR: SELETZ
* REVISED:
*
* Command wrapper for low-level flash erasing
*
*/
static int cmd_flash_erase( int argc, char *argv[] )
{
int ret = 0;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 3 ) return -EINVAL;
ret = strtou32( argv[1], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &len );
if ( ret < 0 ) return -EINVAL;
if ( len & (0x3) ) {
len = (len>>2) + 1;
} else {
len = len>>2;
}
ret = flash_erase_region( (u32 *)dest, len );
return ret;
}
static char flasherasehelp[] = "ferase adr size(bytes)\n"
"erase a flash region\n";
__commandlist( cmd_flash_erase, "ferase", flasherasehelp );
--- NEW FILE: start-pxa.S ---
/*
* start-pxa: PXA (XScale) specific start code
*
* Copyright (C) 2002 Intel Corporation
* Written by Rusty Geldmacher (rus...@in...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
@ We start by implementing *all* exception vectors
@ Reset vector: this initialises the machine
@ note here that this not yet taken sleep wakeup into account -- lets just
@ get something to work first.
.globl reset
reset:
@ First, mask **ALL** interrupts
ldr r0, =ICMR
mov r1, #0x00
str r1, [r0]
real_reset:
#ifdef LUBBOCK
@ Lubbock must initialize GPIO before any chip selects will work.
bl gpio_init
@ now that chip selects will work, turn on lubbock HW registers, SRAM
@ and ethernet contoller chip selects
ldr r3, =MSC1
ldr r2, =MSC1_VAL
str r2, [r3]
ldr r2, [r3] @ need to read it back to latch it
#endif
bl ledinit
@ setup memory
bl memsetup
@ loop here infinitely until I can get this to compile and boot
@ TODO: get this to compile and boot.
crap:
b crap
@ turn off the LED. if it stays off it is an indication that
@ we didnt make it into the C code
bl led_off
@ everything is said and done over here, call normal_boot in
@ the generic startup code to continue the boot procedure
bl normal_boot
@ oops, normal_boot returns, something went wrong. signal an
@ error to the user
mov r6, #2
b endless_blink
/* we could choose to handle all exceptions in a nice way, but the
* best is to treat them as errors because blob should not contain
* errors
*/
/* Undefined instruction exception */
.globl undefined_instruction
undefined_instruction:
mov r6, #3
b endless_blink
/* SWI */
.globl software_interrupt
software_interrupt:
/* NOTE: This is NOT an error! If you think that blob should return
* from software interrupts, you're plain WRONG. The source of the
* problem is in the kernel: you should *disable* CONFIG_ANGELBOOT
* simply because blob is not angel. -- Erik
*/
mov r6, #4
b endless_blink
/* prefetch exception. shouldn't happen though we usually run with
* i-cache enabled */
.globl prefetch_abort
prefetch_abort:
mov r6, #5
b endless_blink
/* data abort */
.globl data_abort
data_abort:
mov r6, #6
b endless_blink
/* we *should* never reach this */
.globl not_used
not_used:
mov r6, #7
b endless_blink
/* interrupt. we could handle this differently later if some kind of
* driver in blob wants to be interrupt driven. for the time being we
* treat it as an error.
*/
.globl irq
irq:
mov r6, #8
b endless_blink
/* FIQ. same as IRQ */
.globl fiq
fiq:
mov r6, #9
b endless_blink
/* endless loop that blinks the LED. r6 contains the number of blinks */
endless_blink:
bl wait
mov r0, r6
bl led_blink
b endless_blink
wait:
/* busy wait loop*/
mov r5, #0x1000000
wait0:
subs r5, r5, #1
bne wait0
mov pc, lr
#ifdef LUBBOCK
@ initialize GPIO. This should be moved to its own file eventually...
init_gpio:
ldr r0, =GPSR0
ldr r1, =0x00008000
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =0x00FC0382
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =0x0001FFFF //0x0001C000
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =0x0060A800
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =0x00FF0382
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =0x0001C000
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =0x98400000
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =0x00002950
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =0x000A9558
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =0x0005AAAA
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =0xA0000000
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =0x00000002
str r1, [r0]
mov pc, lr
#endif
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- Makefile.am 27 May 2002 10:01:50 -0000 1.31
+++ Makefile.am 14 Aug 2002 21:04:23 -0000 1.32
@@ -52,6 +52,9 @@
# ---- Blob first stage loader ---------------------------------------
+.S.o:
+ $(COMPILE) -D__ASSEMBLY__ -c $<
+
# WARNING: start.S *must* be the first file, otherwise the target will
# be linked in the wrong order!
blob_start_elf32_SOURCES = \
@@ -150,7 +153,7 @@
xmodem.c \
accelent_sa.c assabet.c brutus.c badge4.c clart.c frodo.c \
h3600.c idr.c jornada720.c lart.c miniprint.c nesa.c pleb.c \
- shannon.c system3.c trizeps.c
+ shannon.c system3.c trizeps.c pxa_idp.c
blob_rest_elf32_DEPENDENCIES = \
Index: main.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/main.c,v
retrieving revision 1.49
retrieving revision 1.50
diff -u -d -r1.49 -r1.50
--- main.c 2 May 2002 04:16:58 -0000 1.49
+++ main.c 14 Aug 2002 21:04:23 -0000 1.50
@@ -50,7 +50,6 @@
#include <blob/md5support.h>
#include <blob/memory.h>
#include <blob/param_block.h>
-#include <blob/sa1100.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/util.h>
Index: param_block.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/param_block.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- param_block.c 21 Jan 2002 19:45:17 -0000 1.7
+++ param_block.c 14 Aug 2002 21:04:24 -0000 1.8
@@ -40,7 +40,7 @@
#include <blob/param_block.h>
#include <blob/main.h>
#include <blob/util.h>
-#include <blob/sa1100.h>
+
#if (defined(PARAM_START) && !defined(PARAM_LEN))
#error If PARAM_START is defined, PARAM_LEN must be too.
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- start.S 19 Jul 2002 15:20:03 -0000 1.9
+++ start.S 14 Aug 2002 21:04:25 -0000 1.10
@@ -31,7 +31,7 @@
* [2] S. Furber, "ARM System Architecture", Addison Wesley Longman
* Ltd., Essex, England, 1996.
* [3] Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
- * Advanced Developer's manual, December 1999
+ * Advanced Developer's manual", December 1999
*/
.ident "$Id$"
|
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