Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv25657
Modified Files:
memsetup-sa1110.S
Log Message:
prefix register offsets with _ so as to not conflict with sa1100.h defines; add hooks for arch-specific memsetup
Index: memsetup-sa1110.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-sa1110.S,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- memsetup-sa1110.S 19 Apr 2002 20:01:36 -0000 1.13
+++ memsetup-sa1110.S 25 Jul 2002 17:26:41 -0000 1.14
@@ -44,15 +44,43 @@
# include <blob/config.h>
#endif
+#define __ASSEMBLY__
+#include <blob/sa1100.h>
#define BLOB_NEED_MEMCONFIG
#include <blob/memsetup.h>
#include <blob/arch.h>
-
.text
+.globl memsetup
+
MEM_REG_BASE: .long 0xa0000000
MEM_START: .long MEMORY_START
+PWR_BASE: .long 0x90020000
+#define _PSSR 0x04
+#define _PSPR 0x08
+#define _PPCR 0x14
+#define _POSR 0x1C
+
+/* Architecture headers can customized the memory setup behavior with
+ * the following defines:
+ *
+ * ARCH_SPECIFIC_MEMSETUP
+ * arch does its own memort setup. must define memsetup somewhere
+ * which should do whatever it needs to do and do a standard
+ * assembly linkage return (mov pc, lr).
+ *
+ * ARCH_SPECIFIC_MEMSETUP_STD
+ * arch needs std_memsetup procedure. ignored except when
+ * ARCH_SPECIFIC_MEMSETUP is defined.
+ */
+
+
+/* -------------------------------------------------- */
+/* standard memory configuration */
+
+#if !defined(ARCH_SPECIFIC_MEMSETUP) || defined(ARCH_SPECIFIC_MEMSETUP_STD)
+
MEMORY_CONFIG:
.long MDCNFG_VALUE /* 0x0 MDCNFG */
.long MDCAS00_VALUE /* 0x04 MDCAS00 */
@@ -72,40 +100,32 @@
.long MSC2_VALUE /* 0x2C MSC2 */
.long SMCNFG_VALUE /* 0x30 SMCNFG */
-PWR_BASE: .long 0x90020000
-#define PSSR 0x04
-#define PSPR 0x08
-#define PPCR 0x14
-#define POSR 0x1C
-
-.globl memsetup
-memsetup:
- mov r5, lr
-
+.globl std_memsetup
+std_memsetup:
/* Set up the SDRAM */
ldr r0, MEM_REG_BASE
adr r1, MEMORY_CONFIG
- ldr r2, [r1, #MDCNFG ]
- str r2, [r0, #MDCNFG ]
+ ldr r2, [r1, #_MDCNFG ]
+ str r2, [r0, #_MDCNFG ]
- ldr r2, [r1, #MDCAS00 ]
- str r2, [r0, #MDCAS00 ]
+ ldr r2, [r1, #_MDCAS00 ]
+ str r2, [r0, #_MDCAS00 ]
- ldr r2, [r1, #MDCAS01 ]
- str r2, [r0, #MDCAS01 ]
+ ldr r2, [r1, #_MDCAS01 ]
+ str r2, [r0, #_MDCAS01 ]
- ldr r2, [r1, #MDCAS02 ]
- str r2, [r0, #MDCAS02 ]
+ ldr r2, [r1, #_MDCAS02 ]
+ str r2, [r0, #_MDCAS02 ]
- ldr r2, [r1, #MDCAS20 ]
- str r2, [r0, #MDCAS20 ]
+ ldr r2, [r1, #_MDCAS20 ]
+ str r2, [r0, #_MDCAS20 ]
- ldr r2, [r1, #MDCAS21 ]
- str r2, [r0, #MDCAS21 ]
+ ldr r2, [r1, #_MDCAS21 ]
+ str r2, [r0, #_MDCAS21 ]
- ldr r2, [r1, #MDCAS22 ]
- str r2, [r0, #MDCAS22 ]
+ ldr r2, [r1, #_MDCAS22 ]
+ str r2, [r0, #_MDCAS22 ]
/*
* Refer to sections 9.5.3.7: Reviving DRAMS from Self-Refresh Mode
@@ -123,47 +143,47 @@
* NOTE: do NOT clear SSS, the kernel wants it set */
ldr r1, PWR_BASE
mov r2, #0x08 /* PSSR_DH */
- str r2, [r1, #PSSR] /* clear DH by writing 1 to it */
+ str r2, [r1, #_PSSR] /* clear DH by writing 1 to it */
#ifdef MDREFR_DONT_BELIEVE_IN_MAGIC
- ldr r2, [r1, #MDREFR ]
- str r2, [r0, #MDREFR ]
+ ldr r2, [r1, #_MDREFR ]
+ str r2, [r0, #_MDREFR ]
#else
/* clear KxDB2 */
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
bic r2, r2, #MDREFR_K0DB2
bic r2, r2, #MDREFR_K1DB2
bic r2, r2, #MDREFR_K2DB2
bic r2, r2, #0xff /* clear TRASR and DRI */
bic r2, r2, #0xff00
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
/* set TRASR and DRI, KxDB2 */
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
orr r2, r2, #MDREFR_TRASR(7)
orr r2, r2, #MDREFR_DRI(12)
orr r2, r2, #MDREFR_K0DB2
orr r2, r2, #MDREFR_K1DB2
orr r2, r2, #MDREFR_K2DB2
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
/* set KxRUN */
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
orr r2, r2, #MDREFR_K0RUN
orr r2, r2, #MDREFR_K1RUN
orr r2, r2, #MDREFR_K2RUN
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
/* clear SLFRSH */
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
bic r2, r2, #MDREFR_SLFRSH
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
/* toggle E1PIN (set -> clear ) */
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
orr r2, r2, #MDREFR_E1PIN
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
#endif
/* Issue read requests to disabled bank to start refresh */
@@ -176,32 +196,45 @@
adr r1, MEMORY_CONFIG
/* ENABLE SDRAM BANKS */
- ldr r2, [r0, #MDCNFG ]
+ ldr r2, [r0, #_MDCNFG ]
orr r2, r2, #0x00000003
orr r2, r2, #0x00030000
- str r2, [r0, #MDCNFG]
+ str r2, [r0, #_MDCNFG]
/* OPTIONALLY enable Autopowerup/down */
#if 0
- ldr r2, [ r0, #MDREFR ]
+ ldr r2, [ r0, #_MDREFR ]
orr r2, r2, #MDREFR_EAPD
orr r2, r2, #MDREFR_KAPD
- str r2, [ r0, #MDREFR ]
+ str r2, [ r0, #_MDREFR ]
#endif
- ldr r2, [r1, #MCS0 ]
- str r2, [r0, #MCS0 ]
+ ldr r2, [r1, #_MCS0 ]
+ str r2, [r0, #_MCS0 ]
- ldr r2, [r1, #MCS1 ]
- str r2, [r0, #MCS1 ]
+ ldr r2, [r1, #_MCS1 ]
+ str r2, [r0, #_MCS1 ]
- ldr r2, [r1, #MCS2 ]
- str r2, [r0, #MCS2 ]
+ ldr r2, [r1, #_MCS2 ]
+ str r2, [r0, #_MCS2 ]
- ldr r2, [r1, #SMCNFG ]
- str r2, [r0, #SMCNFG ]
+ ldr r2, [r1, #_SMCNFG ]
+ str r2, [r0, #_SMCNFG ]
- ldr r2, [r1, #MECR ]
- str r2, [r0, #MECR ]
+ ldr r2, [r1, #_MECR ]
+ str r2, [r0, #_MECR ]
- mov pc, r5
+ mov pc, lr
+#endif
+
+/* -------------------------------------------------- */
+
+#if !defined(ARCH_SPECIFIC_MEMSETUP)
+memsetup:
+ b std_memsetup
+#endif
+
+
+/* -------------------------------------------------- */
+
+/* Arch specific setup */
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