Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv15720/src/blob
Modified Files:
Makefile.am start.S
Added Files:
start-sa11x0.S
Log Message:
Split up startup code in machine dependent (start-sa11x0.S) and machine
independent part (start.S). Not yet finished, proof of concept that
actually works.
--- NEW FILE: start-sa11x0.S ---
/*
* start-sa11x0.S: StrongARM SA11x0 specific start code
*
* Copyright (C) 1999 2000 2001 2002 Erik Mouw (J.A...@it...) and
* Jan-Derk Bakker (J.D...@it...)
*
* $Id: start-sa11x0.S,v 1.1 2002/01/12 01:45:57 erikm Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/*
* Documentation:
* [1] Intel Corporation, "Intel StrongARM SA-1100 Microprocessor
* Developer's Manual", April 1999
* [2] Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
* Advanced Developer's manual, December 1999
*/
.ident "$Id: start-sa11x0.S,v 1.1 2002/01/12 01:45:57 erikm Exp $"
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
/* some defines to make life easier */
/* Register addresses can be found in [1] Appendix A */
IC_BASE: .word 0x90050000
#define ICMR 0x04
PWR_BASE: .word 0x90020000
#define PSSR 0x04
#define PSPR 0x08
#define PPCR 0x14
RST_BASE: .word 0x90030000
#define RCSR 0x04
/* The initial CPU speed. Note that the SA11x0 CPUs can be safely overclocked:
* 190 MHz CPUs are able to run at 221 MHz, 133 MHz CPUs can do 190 Mhz.
*/
cpuspeed: .word CPU_SPEED
/* We start by implementing *all* exception vectors */
/* Reset vector: this initialises the machine */
.globl reset
reset:
/* First, mask **ALL** interrupts */
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
/* switch CPU to correct speed */
ldr r0, PWR_BASE
ldr r1, cpuspeed
str r1, [r0, #PPCR]
/* init LED */
bl ledinit
/* setup memory */
bl memsetup
/* check if this is a wake-up from sleep */
ldr r0, RST_BASE
ldr r1, [r0, #RCSR]
and r1, r1, #0x0f
teq r1, #0x08
bne normal_boot /* no, continue booting */
/* yes, a wake-up. clear RCSR by writing a 1 (see 9.6.2.1 from [1]) */
mov r1, #0x08
str r1, [r0, #RCSR] ;
/* handle Power Manager Sleep Status Register (PSSR)
* see 9.5.7.5 from [1]*/
ldr r1, [r0, #PSSR]
/* clear DH bit, brings out DRAM from self-refresh */
orr r1, r1, #0x08
/* clear PH bit, bring periperal pins out from sleep state */
orr r1, r1, #0x10
str r1, [r0, #PSSR]
/* get the value from the PSPR and jump to it */
ldr r0, PWR_BASE
ldr r1, [r0, #PSPR]
mov pc, r1
/* everything is said and done over here, call normal_boot in
* the generic startup code to continue the boot procedure */
bl normal_boot
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- Makefile.am 2002/01/07 15:00:14 1.15
+++ Makefile.am 2002/01/12 01:45:57 1.16
@@ -61,10 +61,12 @@
EXTRA_blob_start_elf32_SOURCES = \
memsetup-sa1100.S \
- memsetup-sa1110.S
+ memsetup-sa1110.S \
+ start-sa11x0.S
blob_start_elf32_DEPENDENCIES = \
@MEMSETUP@ \
+ @STARTCODE@ \
start-ld-script
blob_start_elf32_LDFLAGS += \
@@ -72,6 +74,7 @@
blob_start_elf32_LDADD += \
@MEMSETUP@ \
+ @STARTCODE@ \
-lgcc
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- start.S 2001/11/15 11:56:20 1.6
+++ start.S 2002/01/12 01:45:57 1.7
@@ -1,7 +1,7 @@
/*
* start.S: blob start code
*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A...@it...) and
+ * Copyright (C) 1999 2000 2001 2002 Erik Mouw (J.A...@it...) and
* Jan-Derk Bakker (J.D...@it...)
*
* This program is free software; you can redistribute it and/or modify
@@ -55,78 +55,12 @@
b irq
b fiq
-
-
-
/* some defines to make life easier */
-/* Register addresses can be found in [1] Appendix A */
-IC_BASE: .word 0x90050000
-#define ICMR 0x04
-
-PWR_BASE: .word 0x90020000
-#define PSSR 0x04
-#define PSPR 0x08
-#define PPCR 0x14
-
-RST_BASE: .word 0x90030000
-#define RCSR 0x04
-
/* main memory starts at 0xc0000000 */
BLOB_START: .word BLOB_ABS_BASE_ADDR
-
-/* The initial CPU speed. Note that the SA11x0 CPUs can be safely overclocked:
- * 190 MHz CPUs are able to run at 221 MHz, 133 MHz CPUs can do 190 Mhz.
- */
-cpuspeed: .word CPU_SPEED
-
-
-
-/* the actual reset code */
-reset:
- /* First, mask **ALL** interrupts */
- ldr r0, IC_BASE
- mov r1, #0x00
- str r1, [r0, #ICMR]
-
- /* switch CPU to correct speed */
- ldr r0, PWR_BASE
- ldr r1, cpuspeed
- str r1, [r0, #PPCR]
-
-
- /* init LED */
- bl ledinit
-
- /* setup memory */
- bl memsetup
-
- /* check if this is a wake-up from sleep */
- ldr r0, RST_BASE
- ldr r1, [r0, #RCSR]
- and r1, r1, #0x0f
- teq r1, #0x08
- bne normal_boot /* no, continue booting */
- /* yes, a wake-up. clear RCSR by writing a 1 (see 9.6.2.1 from [1]) */
- mov r1, #0x08
- str r1, [r0, #RCSR] ;
-
- /* handle Power Manager Sleep Status Register (PSSR)
- * see 9.5.7.5 from [1]*/
- ldr r1, [r0, #PSSR]
- /* clear DH bit, brings out DRAM from self-refresh */
- orr r1, r1, #0x08
- /* clear PH bit, bring periperal pins out from sleep state */
- orr r1, r1, #0x10
- str r1, [r0, #PSSR]
-
- /* get the value from the PSPR and jump to it */
- ldr r0, PWR_BASE
- ldr r1, [r0, #PSPR]
- mov pc, r1
-
-
+.globl normal_boot
normal_boot:
/* check the first 1MB of BLOB_START in increments of 4k */
mov r7, #0x1000
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