blob-cvs-commit

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv6433

Modified Files:
	assabet.h clart.h h3600.h system3.h 
Log Message:
- added system dependent memory configuration (used in memsetup-sa1110.S)


Index: assabet.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/assabet.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- assabet.h	2001/10/14 20:24:32	1.1
+++ assabet.h	2001/10/29 11:36:45	1.2
@@ -28,6 +28,7 @@
 
 
 
+#include <blob/memsetup.h>
 
 
 /* boot CPU speed */
@@ -58,7 +59,23 @@
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(8 * 1024)
 
-
 
+/* Memory configuration */
+#ifdef BLOB_NEED_MEMCONFIG
+#warning "use defines from memsetup.h for better readability"
+#	define MDCNFG_VALUE	0x72547254		/* 0x0  MDCNFG */
+#	define MDCAS00_VALUE	0xAAAAAA7F		/* 0x04 MDCAS00 */
+#	define MDCAS01_VALUE	0xAAAAAAAA		/* 0x08 MDCAS01 */
+#	define MDCAS02_VALUE	0xAAAAAAAA		/* 0x0c MDCAS02 */
+#	define MSC0_VALUE	0x4b384370		/* 0x10 MCS0 */
+#	define MSC1_VALUE	0x22212419		/* 0x14 MCS1 */
+#	define MECR_VALUE	0x994a994a		/* 0x18 MECR */
+#	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
+#	define MDCAS20_VALUE	0xAAAAAA7F		/* 0x20 MDCAS20 */
+#	define MDCAS21_VALUE	0xAAAAAAAA		/* 0x24 MDCAS21 */
+#	define MDCAS22_VALUE	0xAAAAAAAA		/* 0x28 MDCAS22 */
+#	define MSC2_VALUE	0x42196669		/* 0x2C MCS2 */
+#	define SMCNFG_VALUE	0xafccafcc		/* 0x30 SMCNFG */
+#endif
 
 #endif

Index: clart.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/clart.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- clart.h	2001/10/14 20:24:32	1.1
+++ clart.h	2001/10/29 11:36:45	1.2
@@ -26,39 +26,45 @@
 #ifndef BLOB_ARCH_CLART_H
 #define BLOB_ARCH_CLART_H
 
-
-
-
-
 /* boot CPU speed */
 #define CPU_SPEED		(0x0b)
 
-
 /* GPIO for the LED */
 #define LED_GPIO		(0x00800000) /* GPIO 23 */
 
-
 /* where do various parts live in RAM */
 #define BLOB_RAM_BASE		(0xc0100000)
 #define KERNEL_RAM_BASE		(0xC0008000)
 #define PARAM_RAM_BASE		(0xc0110000)
 #define RAMDISK_RAM_BASE	(0xC0400000)
 
-
 /* and where do they live in flash */
 #define BLOB_BLOCK_OFFSET	(0x00000000)
 #define KERNEL_BLOCK_OFFSET	(0x00008000)
 #define RAMDISK_BLOCK_OFFSET	(0x00400000)
 
-
 /* the position of the kernel boot parameters */
 #define BOOT_PARAMS		(0xc0000100)
 
-
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(8 * 1024)
-
-
 
+/* Memory configuration */
+#ifdef BLOB_NEED_MEMCONFIG
+#warning "use defines from memsetup.h for better readability"
+#	define MDCNFG_VALUE	0x72547254		/* 0x0  MDCNFG */
+#	define MDCAS00_VALUE	0xAAAAAA7F		/* 0x04 MDCAS00 */
+#	define MDCAS01_VALUE	0xAAAAAAAA		/* 0x08 MDCAS01 */
+#	define MDCAS02_VALUE	0xAAAAAAAA		/* 0x0c MDCAS02 */
+#	define MSC0_VALUE	0x4b384370		/* 0x10 MCS0 */
+#	define MSC1_VALUE	0x22212419		/* 0x14 MCS1 */
+#	define MECR_VALUE	0x994a994a		/* 0x18 MECR */
+#	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
+#	define MDCAS20_VALUE	0xAAAAAA7F		/* 0x20 MDCAS20 */
+#	define MDCAS21_VALUE	0xAAAAAAAA		/* 0x24 MDCAS21 */
+#	define MDCAS22_VALUE	0xAAAAAAAA		/* 0x28 MDCAS22 */
+#	define MSC2_VALUE	0x42196669		/* 0x2C MCS2 */
+#	define SMCNFG_VALUE	0xafccafcc		/* 0x30 SMCNFG */
+#endif
 
 #endif

Index: h3600.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/h3600.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- h3600.h	2001/10/27 21:04:20	1.1
+++ h3600.h	2001/10/29 11:36:45	1.2
@@ -26,10 +26,6 @@
 #ifndef BLOB_ARCH_H3600_H
 #define BLOB_ARCH_H3600_H
 
-
-
-
-
 /* boot CPU speed */
 #define CPU_SPEED		(0x0a)
 
@@ -57,8 +53,23 @@
 
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(8 * 1024)
-
-
 
+/* Memory configuration */
+#ifdef BLOB_NEED_MEMCONFIG
+#warning "use defines from memsetup.h for better readability"
+#	define MDCNFG_VALUE	0x72547254		/* 0x0  MDCNFG */
+#	define MDCAS00_VALUE	0xAAAAAA7F		/* 0x04 MDCAS00 */
+#	define MDCAS01_VALUE	0xAAAAAAAA		/* 0x08 MDCAS01 */
+#	define MDCAS02_VALUE	0xAAAAAAAA		/* 0x0c MDCAS02 */
+#	define MSC0_VALUE	0x4b384370		/* 0x10 MCS0 */
+#	define MSC1_VALUE	0x22212419		/* 0x14 MCS1 */
+#	define MECR_VALUE	0x994a994a		/* 0x18 MECR */
+#	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
+#	define MDCAS20_VALUE	0xAAAAAA7F		/* 0x20 MDCAS20 */
+#	define MDCAS21_VALUE	0xAAAAAAAA		/* 0x24 MDCAS21 */
+#	define MDCAS22_VALUE	0xAAAAAAAA		/* 0x28 MDCAS22 */
+#	define MSC2_VALUE	0x42196669		/* 0x2C MCS2 */
+#	define SMCNFG_VALUE	0xafccafcc		/* 0x30 SMCNFG */
+#endif
 
 #endif

Index: system3.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/system3.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- system3.h	2001/10/14 20:24:32	1.1
+++ system3.h	2001/10/29 11:36:45	1.2
@@ -26,12 +26,14 @@
 #ifndef BLOB_ARCH_SYSTEM3_H
 #define BLOB_ARCH_SYSTEM3_H
 
-
-
-
+#undef	CPU_SPEED_133
 
 /* boot CPU speed */
-#define CPU_SPEED		(0x05)
+#ifdef CPU_SPEED_133
+#	define CPU_SPEED		(0x05)
+#else
+#	define CPU_SPEED		(0x0a)
+#endif
 
 
 /* GPIO for the LED */
@@ -59,6 +61,49 @@
 #define RAMDISK_SIZE		(8 * 1024)
 
 
+/* Memory configuration */
+#ifdef BLOB_NEED_MEMCONFIG
+#define MSC0_VALUE_66_150     MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(10) | MSC_RDN(2) | MSC_RRR(1)
+#define MSC0_VALUE_66_120     MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 8) | MSC_RDN(2) | MSC_RRR(1)
+#define MSC0_VALUE_66_100     MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 7) | MSC_RDN(2) | MSC_RRR(1)
+#define MSC1_VALUE_66         MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1) | ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
+#define MSC2_VALUE_66         MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(7)  | MSC_RDN(2) | MSC_RRR(1)
+#define MECR_VALUE_66         0
+#define MSC0_VALUE_100_150    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(16) | MSC_RDN(3) | MSC_RRR(2)
+#define MSC0_VALUE_100_120    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2)
+#define MSC0_VALUE_100_100    MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2)
+#define MSC1_VALUE_100        MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
+#define MSC2_VALUE_100        MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9)  | MSC_RDN(2) | MSC_RRR(1)
+#define MECR_VALUE_100        0
+
+#ifndef CPU_SPEED_133
+//	206 Mhz
+#	define MDCAS00_VALUE	0xAAAAAA9F
+#	define MDCAS01_VALUE	0xAAAAAAAA
+#	define MDCAS02_VALUE	0xAAAAAAAA
+#	define MDCAS20_VALUE	0xAAAAAA9F
+#	define MDCAS21_VALUE	0xAAAAAAAA
+#	define MDCAS22_VALUE	0xAAAAAAAA
+#	define MSC0_VALUE	MSC0_VALUE_100_150
+#	define MSC1_VALUE	MSC1_VALUE_100
+#	define MSC2_VALUE	MSC2_VALUE_100
+#	define MECR_VALUE	MECR_VALUE_100
+#	define SMCNFG_VALUE	0
+#else
+//	133 Mhz
+#	define MDCAS00_VALUE	0xAAAAAA9F
+#	define MDCAS01_VALUE	0xAAAAAAAA
+#	define MDCAS02_VALUE	0xAAAAAAAA
+#	define MDCAS20_VALUE	0xAAAAAA9F
+#	define MDCAS21_VALUE	0xAAAAAAAA
+#	define MDCAS22_VALUE	0xAAAAAAAA
+#	define MSC0_VALUE	MSC0_VALUE_66_150
+#	define MSC1_VALUE	MSC1_VALUE_66
+#	define MSC2_VALUE	MSC2_VALUE_66
+#	define MECR_VALUE	MECR_VALUE_66
+#	define SMCNFG_VALUE	0
+#endif
+#endif
 
 
 #endif