Update of /cvsroot/blob/blob/src
In directory usw-pr-cvs1:/tmp/cvs-serv23106
Modified Files:
memsetup-sa1110.S
Log Message:
- largely reworked for multiple board support
- perform SA1110 Hardware Reset Procedure
Index: memsetup-sa1110.S
===================================================================
RCS file: /cvsroot/blob/blob/src/memsetup-sa1110.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- memsetup-sa1110.S 2001/09/23 15:01:18 1.2
+++ memsetup-sa1110.S 2001/10/04 12:23:08 1.3
@@ -29,6 +29,10 @@
* appears to be true, but it might be possible that somebody designs a
* board with mixed EDODRAM/SDRAM memory. -- Erik
*
+ * 04-10-2001: SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
*/
.ident "$Id$"
@@ -37,95 +41,170 @@
# include <config.h>
#endif
+#include <memsetup.h>
-
-
.text
-
-
-
-
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-#define MDCNFG 0x0
-#define MDCAS0 0x04
-#define MDCAS1 0x08
-#define MDCAS2 0x0c
-#define MCS0 0x10
+MEM_REG_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
-
-
+#ifdef ASSABET
+ .align 4
+MEMORY_CONFIG:
+ .long 0x72547254 /* 0x0 MDCNFG */
+ .long 0xAAAAAA7F /* 0x04 MDCAS00 */
+ .long 0xAAAAAAAA /* 0x08 MDCAS01 */
+ .long 0xAAAAAAAA /* 0x0c MDCAS02 */
+ .long 0x4b904b90 /* 0x10 MCS0 */
+ .long 0x22212419 /* 0x14 MCS1 */
+ .long 0x994a994a /* 0x18 MECR */
+ .long 0x4dbc0317 /* 0x1C MDREFR */
+ .long 0xAAAAAA7F /* 0x20 MDCAS20 */
+ .long 0xAAAAAAAA /* 0x24 MDCAS21 */
+ .long 0xAAAAAAAA /* 0x28 MDCAS22 */
+ .long 0x42196669 /* 0x2C MCS2 */
+ .long 0xafccafcc /* 0x30 SMCNFG */
+MEMORY_CONFIG_END:
+ .long 0x0
+
+#elif defined PT_SYSTEM3
+ .align 4
+MEMORY_CONFIG:
+ .long 0x72547254 /* 0x0 MDCNFG */
+ .long 0xAAAAAA7F /* 0x04 MDCAS00 */
+ .long 0xAAAAAAAA /* 0x08 MDCAS01 */
+ .long 0xAAAAAAAA /* 0x0c MDCAS02 */
+ .long 0x00004380 /* 0x10 MCS0 */
+ .long 0xfef5212c /* 0x14 MCS1 */
+ .long 0x994a994a /* 0x18 MECR */
+ .long 0x023600c1 /* 0x1C MDREFR */
+ .long 0xAAAAAA7F /* 0x20 MDCAS20 */
+ .long 0xAAAAAAAA /* 0x24 MDCAS21 */
+ .long 0xAAAAAAAA /* 0x28 MDCAS22 */
+ .long 0x00002249 /* 0x2C MCS2 */
+ .long 0xafccafcc /* 0x30 SMCNFG */
+MEMORY_CONFIG_END:
+ .long 0x0
+#else
+# error "add memory config for your board!"
+#endif
.globl memsetup
memsetup:
- /* This part is actually for the Assabet only. If your board
- * uses other settings, you'll have to ifdef them here.
- */
- /* Set up the SDRAM */
- mov r1, #0xA0000000 /* MDCNFG base address */
-
- ldr r2, =0xAAAAAA7F
- str r2, [r1, #0x04] /* MDCAS00 */
- str r2, [r1, #0x20] /* MDCAS20 */
+ mov r5, lr
+ bl ledinit
+ bl led_on
- ldr r2, =0xAAAAAAAA
- str r2, [r1, #0x08] /* MDCAS01 */
- str r2, [r1, #0x24] /* MDCAS21 */
+ /* Set up the SDRAM */
+ ldr r0, MEM_REG_BASE
+ adr r1, MEMORY_CONFIG
- ldr r2, =0xAAAAAAAA
- str r2, [r1, #0x0C] /* MDCAS02 */
- str r2, [r1, #0x28] /* MDCAS22 */
+ ldr r2, [r1, #MDCNFG ]
+ str r2, [r0, #MDCNFG ]
- ldr r2, =0x4dbc0327 /* MDREFR */
- str r2, [r1, #0x1C]
+ ldr r2, [r1, #MDCAS00 ]
+ str r2, [r0, #MDCAS00 ]
- ldr r2, =0x72547254 /* MDCNFG */
- str r2, [r1, #0x00]
+ ldr r2, [r1, #MDCAS01 ]
+ str r2, [r0, #MDCAS01 ]
+
+ ldr r2, [r1, #MDCAS02 ]
+ str r2, [r0, #MDCAS02 ]
+
+ ldr r2, [r1, #MDCAS20 ]
+ str r2, [r0, #MDCAS20 ]
+
+ ldr r2, [r1, #MDCAS21 ]
+ str r2, [r0, #MDCAS21 ]
+
+ ldr r2, [r1, #MDCAS22 ]
+ str r2, [r0, #MDCAS22 ]
+
+#if 1
+ /* clear K1DB2 K2DB2 */
+ ldr r2, [ r0, #MDREFR ]
+ bic r2, r2, #MDREFR_K1DB2
+ //bic r2, r2, #MDREFR_K2DB2
+ str r2, [ r0, #MDREFR ]
+
+ /* set TRASR and DRI, K1DB2 K2DB2 */
+ ldr r2, [ r0, #MDREFR ]
+ orr r2, r2, #MDREFR_TRASR(7)
+ orr r2, r2, #MDREFR_DRI(12)
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ str r2, [ r0, #MDREFR ]
+
+ /* set K1RUN K2RUN */
+ ldr r2, [ r0, #MDREFR ]
+ orr r2, r2, #MDREFR_K1RUN
+ orr r2, r2, #MDREFR_K2RUN
+ str r2, [ r0, #MDREFR ]
+
+ /* clear SLFRSH */
+ ldr r2, [ r0, #MDREFR ]
+ bic r2, r2, #MDREFR_SLFRSH
+ str r2, [ r0, #MDREFR ]
+
+ /* toggle E1PIN (set -> clear ) */
+ ldr r2, [ r0, #MDREFR ]
+ orr r2, r2, #MDREFR_E1PIN
+ str r2, [ r0, #MDREFR ]
+#else
+ ldr r2, [ r1, #MDREFR ]
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ //orr r2, r2, #MDREFR_EAPD
+ //orr r2, r2, #MDREFR_KAPD
+ str r2, [ r0, #MDREFR ]
+#endif
/* Issue read requests to disabled bank to start refresh */
-
ldr r1, =0xC0000000
-
.rept 8
ldr r0, [r1]
.endr
- mov r1, #0xA0000000 /* MDCNFG base address */
+ ldr r0, MEM_REG_BASE
+ adr r1, MEMORY_CONFIG
- ldr r2, =0x72547255 /* Enable the banks */
- str r2, [r1, #0x00] /* MDCNFG */
-
-/* Static memory chip selects on Assabet: */
-
- ldr r2, =0x4b90 /* MCS0 */
- orr r2,r2,r2,lsl #16
- str r2, [r1, #0x10]
-
- ldr r2, =0x22212419 /* MCS1 */
- str r2, [r1, #0x14]
-
- ldr r2, =0x42196669 /* MCS2 */
- str r2, [r1, #0x2C]
-
- ldr r2, =0xafccafcc /* SMCNFG */
- str r2, [r1, #0x30]
+ /* ENABLE SDRAM BANKS */
+ ldr r2, [r0, #MDCNFG ]
+#if defined ASSABET
+ orr r2, r2, #0x00000001 /* BANK 0 */
+ // orr r2, r2, #0x00000002 /* BANK 1 */
+ // orr r2, r2, #0x00010000 /* BANK 2 */
+ // orr r2, r2, #0x00020000 /* BANK 3 */
+#elif defined PT_SYSTEM3
+ orr r2, r2, #0x00000001 /* BANK 0 */
+ // orr r2, r2, #0x00000002 /* BANK 1 */
+ orr r2, r2, #0x00010000 /* BANK 2 */
+ // orr r2, r2, #0x00020000 /* BANK 3 */
+#else
+# error "Enable SDRAM Banks on your board!"
+#endif
+ str r2, [r0, #MDCNFG]
-/* Set up PCMCIA space */
+ /* OPTIONALLY enable Autopowerup/down */
+#if defined PT_SYSTEM3
+ ldr r2, [ r0, #MDREFR ]
+ orr r2, r2, #MDREFR_EAPD
+ orr r2, r2, #MDREFR_KAPD
+ str r2, [ r0, #MDREFR ]
+#endif
- ldr r2, =0x994a994a
- str r2, [r1, #0x18]
+ ldr r2, [r1, #MCS0 ]
+ str r2, [r0, #MCS0 ]
-/* All SDRAM memory settings should be ready to go... */
-/* For best performance, should fill out remaining memory config regs: */
+ ldr r2, [r1, #MCS1 ]
+ str r2, [r0, #MCS1 ]
+ ldr r2, [r1, #MECR ]
+ str r2, [r0, #MECR ]
- /* Testing ,Chester */
- mov r3,#0x12000000
- mov r2,#0x5000 /* D9_LED on and D8_LED off */
- str r2,[r3]
- mov r4, #0x20000
-gogogo2:
- subs r4, r4, #1
- bne gogogo2
+ ldr r2, [r1, #MCS2 ]
+ str r2, [r0, #MCS2 ]
+
+ mov r2, #3
+ bl led_blink
- mov pc, lr
+ mov pc, r5
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