Update of /cvsroot/blob/blob/src
In directory usw-pr-cvs1:/tmp/cvs-serv29015/src
Modified Files:
Tag: blob_1_0_9_hack
main.c start.S
Log Message:
initial SHANNON patches
Index: main.c
===================================================================
RCS file: /cvsroot/blob/blob/src/main.c,v
retrieving revision 1.1.1.1.2.2
retrieving revision 1.1.1.1.2.3
diff -u -r1.1.1.1.2.2 -r1.1.1.1.2.3
--- main.c 2001/07/03 20:44:34 1.1.1.1.2.2
+++ main.c 2001/07/07 19:24:40 1.1.1.1.2.3
@@ -230,6 +230,9 @@
#elif defined PLEB
#warning "This is NOT the correct PLEB architecture number!"
theKernel(0, 18);
+#elif defined SHANNON
+#warning "This is NOT the correct SHANNON architecture number!"
+ theKernel(0, 18);
#else
/* Be generic and just tell the kernel that we are an SA1100
architecture */
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/start.S,v
retrieving revision 1.1.1.1.2.2
retrieving revision 1.1.1.1.2.3
diff -u -r1.1.1.1.2.2 -r1.1.1.1.2.3
--- start.S 2001/07/03 20:44:34 1.1.1.1.2.2
+++ start.S 2001/07/07 19:24:40 1.1.1.1.2.3
@@ -78,13 +78,21 @@
mov r2, #0x00
str r2, [r1, #0x4]
-
+#if defined SHANNON
+ /* Switch the CPU to 206.4 MHz by writing the PPCR. */
+ /* Don't worry, 206.4 MHz is also safe for 133 MHz CPUs. */
+ mov r1, #0x90000000
+ add r1, r1, #0x20000
+ mov r2, #0x0a
+ str r2, [r1, #0x14]
+#else
/* Switch the CPU to 221 MHz by writing the PPCR. */
/* Don't worry, 221 MHz is also safe for 190 MHz CPUs. */
mov r1, #0x90000000
add r1, r1, #0x20000
mov r2, #0x0b
str r2, [r1, #0x14]
+#endif
/* Enable I-cache */
mrc p15, 0, r1, c1, c0, 0 @ read control reg
@@ -126,10 +134,23 @@
mov r2, #0x03000000
add r2, r2, #0x00340000
add r2, r2, #0x0000B200
+#ifdef SHANNON
+ add r2, r2, #0x0000001f
+#else
add r2, r2, #0x0000002f
+#endif
str r2, [r1, #0x00]
+#ifdef SHANNON
+ /* Issue read requests to disabled bank to start refresh */
+ ldr r1, =0xC0000000
+ /* this is required by the Micron memory on a TuxScreen */
+.rept 8
+ ldr r0, [r1]
+.endr
+#endif
+
#elif defined USE_SA1110
/* This part is actually for the Assabet only. If your board
@@ -236,19 +257,26 @@
mov r2, #0x08
str r2, [r1, #0x00]
+ /* Set BRD to 1, for a baudrate of 115k2 ([1] 11.11.4.1) */
/* Set BRD to 5, for a baudrate of 38k4 ([1] 11.11.4.1) */
/* Set BRD to 23, for a baudrate of 9k6 ([1] 11.11.4.1) */
mov r2, #0x00
str r2, [r1, #0x04]
+#ifdef SHANNON
+ mov r2, #1
+#else
mov r2, #23
+#endif
str r2, [r1, #0x08]
/* Initialize the GPDR (GPIO Pin Direction Register) in such a
way that the LED is on an output port */
+#ifndef SHANNON
/* load the GPIO base in r2 */
mov r2, #0x90000000
add r2, r2, #0x40000
+#endif
#if defined ASSABET
/* Bit 17 is the LED on Zilker */
@@ -277,6 +305,8 @@
#elif defined PLEB
#warning "FIXME: Include code to turn on one of the PLEB LEDs over here"
+#elif defined SHANNON
+#warning "FIXME: Include code to turn on one of the SHANNON LEDs over here"
#else
#warning "FIXME: Include code to turn on one of the LEDs on your board"
#endif
@@ -316,6 +346,17 @@
adr r0, int_flash_str
bl print_str
+#elif defined SHANNON
+ mov r1, #0xA0000000
+ /* Put the main flash to the correct speed */
+ mov r2, #0xAD000000
+ add r2, r2, #0x008C0000
+ add r2, r2, #0x00004800
+ add r2, r2, #0x00000088
+ str r2, [r1, #0x10]
+
+ adr r0, int_flash_str
+ bl print_str
#endif
#if defined NESA
@@ -330,6 +371,10 @@
bl print_str
#endif
+#ifdef SHANNON
+ /* Skip the memory zeroing for speed */
+ b zero_done
+#endif
test_mem:
/* Start the memory tester, hardcoded bank 0 & 1 for now */
adr r0, start_test
@@ -373,6 +418,7 @@
adr r0, zeroing_done
bl print_str
+zero_done:
mov r4, #0xC0000000
mov r5, #0xD0000000
mov r6, r4 /* Base for current block */
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