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From: Holger S. <hol...@us...> - 2003-08-15 06:28:34
|
Update of /cvsroot/blob/blob/src/lib
In directory sc8-pr-cvs1:/tmp/cvs-serv14195/src/lib
Modified Files:
Makefile.am
Log Message:
support for new autoconf/automake
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/Makefile.am,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- Makefile.am 6 Aug 2003 22:55:41 -0000 1.28
+++ Makefile.am 15 Aug 2003 06:18:57 -0000 1.29
@@ -92,7 +92,7 @@
@BLOB_CF_OBJS@ \
@BLOB_GIO_OBJS@
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include
|
|
From: Holger S. <hol...@us...> - 2003-08-15 06:28:34
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv14195/src/blob
Modified Files:
Makefile.am
Log Message:
support for new autoconf/automake
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.40
retrieving revision 1.41
diff -u -d -r1.40 -r1.41
--- Makefile.am 6 Aug 2003 22:55:41 -0000 1.40
+++ Makefile.am 15 Aug 2003 06:18:57 -0000 1.41
@@ -28,7 +28,7 @@
blob
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include \
-I${LINUX_INCLUDE}
@@ -106,12 +106,13 @@
rest-ld-script
-blob_rest_elf32_LDFLAGS += \
+blob_rest_elf32_LDFLAGS = \
+ -static -nostdlib \
-Wl,-T,rest-ld-script \
-Wl,-Map,blob-rest-elf32.map
-blob_rest_elf32_LDADD += \
+blob_rest_elf32_LDADD = \
@BLOB_CHKMEM_OBJS@ \
@BLOB_CLOCK_OBJS@ \
@BLOB_CRAMFS_OBJS@ \
@@ -163,11 +164,12 @@
start-ld-script \
blob-rest-piggy.o
-blob_elf32_LDFLAGS += \
+blob_elf32_LDFLAGS = \
+ -static -nostdlib \
-Wl,-T,${srcdir}/start-ld-script \
-Wl,-Map,blob-start-elf32.map
-blob_elf32_LDADD += \
+blob_elf32_LDADD = \
@BLOB_LED_STARTCODE@ \
@BLOB_MEMSETUP_OBJS@ \
@BLOB_STARTCODE_OBJS@ \
|
|
From: Holger S. <hol...@us...> - 2003-08-15 06:22:54
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv14645/src/blob
Added Files:
ramses.c
Log Message:
Ramses support
--- NEW FILE: ramses.c ---
/*
* ramses: M%N Ramses MN-CI stuff
*
* Copyright (C) 2001 Erik Mouw (J.A...@it...)
* Copyright (C) 2001 Stefan Eletzhofer
* (ste...@ww...)
* Copyright (C) 2002 Jeff Sutherland <je...@ac...>
* Copyright (C) 2003 Holger Schurig <h.s...@mn...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/**********************************************************************
* includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/main.h>
#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/util.h>
#include <blob/serial.h>
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/command.h>
#include <blob/uucodec.h>
#include <blob/serial.h>
extern blob_status_t blob_status;
/* flash descriptor for Ramses MN-CI flash. */
/* Ramses uses 2xINTEL e28F128 Chips */
static const flash_descriptor_t ramses_flash_descriptors[] =
{
{
size: 2 * 128 * 1024,
num: 128,
lockable: 1
},
{
/* NULL block */
},
};
static int ramses_flash_enable_vpp(void)
{
//TODO
return 0;
}
static int ramses_flash_disable_vpp(void)
{
//TODO
return 0;
}
static void init_ramses_flash_driver(void)
{
flash_descriptors = ramses_flash_descriptors;
flash_driver = &intel32_flash_driver;
flash_driver->enable_vpp = ramses_flash_enable_vpp;
flash_driver->disable_vpp = ramses_flash_disable_vpp;
}
__initlist(init_ramses_flash_driver, INIT_LEVEL_DRIVER_SELECTION);
static void ramses_init_hardware(void)
{
/* select serial driver */
serial_driver = &pxa_serial_driver;
}
__initlist(ramses_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
|
|
From: Holger S. <hol...@us...> - 2003-08-15 06:22:53
|
Update of /cvsroot/blob/blob/src/diag
In directory sc8-pr-cvs1:/tmp/cvs-serv14645/src/diag
Added Files:
ramses.c
Log Message:
Ramses support
--- NEW FILE: ramses.c ---
/**********************************************************************
* ramses.c
*
* Implements several POST routines for M&N Ramses MN-CI
*
* Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
* Copyright (c) 2002 Jeff Sutherland <je...@ac...>
* Copyright (c) 2003 Holger Schurig <h.s...@mn...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/**********************************************************************
* Includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/types.h>
#include <blob/errno.h>
#include <blob/util.h>
#include <blob/command.h>
#include <blob/init.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/arch.h>
#define MEM(adr) (*((u32*)adr))
#define SET(reg,bit) ((reg) |= (1<<(bit)))
#define CLR(reg,bit) ((reg) &= ~(1<<(bit)))
static void ramses_init_hardware(void)
{
/* select serial driver */
// also have to set up all gpio's here as well
serial_driver = &pxa_serial_driver;
}
__initlist(ramses_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
|
|
From: Holger S. <hol...@us...> - 2003-08-15 06:22:53
|
Update of /cvsroot/blob/blob/include/blob/arch In directory sc8-pr-cvs1:/tmp/cvs-serv14645/include/blob/arch Added Files: ramses.h Log Message: Ramses support --- NEW FILE: ramses.h --- /* * ramses.h: M&N Ramses MN-CI * * Copyright (C) 2001 Erik Mouw (J.A...@it...) * Copyright (c) 2002 Jeff Sutherland <je...@ac...> * Copyright (C) 2003 Holger Schurig <h.s...@mn...> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #ifndef BLOB_ARCH_RAMSES_H #define BLOB_ARCH_RAMSES_H /* speed definitions are more complex on Xscale- need core, internal bus, * and memory numbers. Not all combinations are valid. */ #undef CPU_SPEED_400 /* boot CPU speed */ #ifdef CPU_SPEED_100 # define CPU_SPEED (0x05) #else # define CPU_SPEED (0x0a) #endif #define USE_SERIAL1 #define TERMINAL_SPEED baud_115200 /* the base address were BLOB is loaded by the first stage loader */ #define BLOB_ABS_BASE_ADDR (0xa0200400) /* where do various parts live in RAM */ #define BOOT_PARAMS (0xa0000100) #define BLOB_RAM_BASE (0xa0100000) #define PARAM_RAM_BASE (0xa0200000) #define KERNEL_RAM_BASE (0xa0800000) //#define RAMDISK_RAM_BASE (0xa1000000) /* and where do they live in flash */ #define BLOB_FLASH_BASE (0x00000000) #define BLOB_FLASH_LEN (256 * 1024) #define PARAM_FLASH_BASE (BLOB_FLASH_BASE + BLOB_FLASH_LEN) #define PARAM_FLASH_LEN (256 * 1024) #define KERNEL_FLASH_BASE (PARAM_FLASH_BASE + PARAM_FLASH_LEN) #define KERNEL_FLASH_LEN (1024 * 1024) //#define RAMDISK_FLASH_BASE (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN) //#define RAMDISK_FLASH_LEN (4 * 1024 * 1024) /* this needs to be defined if you want parameter block support */ #define PARAM_START PARAM_FLASH_BASE #define PARAM_LEN PARAM_FLASH_LEN /* load ramdisk into ram */ #define LOAD_RAMDISK 0 /* the size (in kbytes) to which the compressed ramdisk expands */ //#define RAMDISK_SIZE (4 * 1024) /* #ifdef BLOB_NEED_MEMCONFIG */ /* this is full tilt boogie (400MHz cpu, 100Mhz mem, 100MHz clk) #define MDCNFG_VALUE 0x0A000AC9 #define MDREFR_VALUE 0x0085C017 #define MSC0_VALUE 0x29DCA4D2 #define MSC1_VALUE 0x439C493C #define MSC2_VALUE 0x7FD449D1 #define MECR_VALUE 0x00000003 */ /* I took these from the Lubbock setup, they should probably be changed * for actual IDP values, but these are there for now :-) */ #define PERIF_BASE_PHYSICAL 0x40000000 #define MEMC_BASE_PHYSICAL 0x48000000 #define SDRAM_BASE_PHYSICAL 0xA0000000 #define OST_OFFSET 0x00A00000 #define OSCR_OFFSET 0x10 #define OST_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + OST_OFFSET) #define OSCR_BASE_PHYSICAL (OST_BASE_PHYSICAL + OSCR_OFFSET) #define MSC0_VAL 0x23F223F2 #define MSC1_VAL 0x3FF1A441 #define MSC2_VAL 0x7FF17FF1 #define MECR_VAL 0x00000000 #define MCMEM0_VAL 0x00010504 #define MCMEM1_VAL 0x00010504 #define MCATT0_VAL 0x00010504 #define MCATT1_VAL 0x00010504 #define MCIO0_VAL 0x00004715 #define MCIO1_VAL 0x00004715 #define MDREFR_VAL 0x00018018 #define MDCNFG_VAL 0x00001AC9 #define MDMRS_VAL 0x00000000 /* Debugging macros used in accelent code */ #define RAMSES_DEBUG 1 #ifdef RAMSES_DEBUG # define _DBGU32( x ) SerialOutputString( #x"=0x" ); \ SerialOutputHex( (u32)x ); \ serial_write( '\n' ); #else # define _DBGU32( x ) #endif #endif |
|
From: Holger S. <hol...@us...> - 2003-08-15 06:22:53
|
Update of /cvsroot/blob/blob In directory sc8-pr-cvs1:/tmp/cvs-serv14645 Modified Files: ChangeLog Log Message: Ramses support Index: ChangeLog =================================================================== RCS file: /cvsroot/blob/blob/ChangeLog,v retrieving revision 1.25 retrieving revision 1.26 diff -u -d -r1.25 -r1.26 --- ChangeLog 15 Aug 2003 06:18:57 -0000 1.25 +++ ChangeLog 15 Aug 2003 06:21:44 -0000 1.26 @@ -8,6 +8,7 @@ (NOTE: Please add new entries at the top, not at the bottom) +- Ramses support Holger Schurig - using new autoconf/automake Holger Schurig - made it fully PXA compatible Abraham van der Merwe - CSIR IMS support Abraham van der Merwe |
|
From: Holger S. <h.s...@mn...> - 2003-08-14 10:24:16
|
Hi all ! I have a bunch of updates to make blob-cvs work with the newest autoconf/autoheader/automake. E.g. I'm fixing in som files: * += to = * CFLAGS to programname_CFLAGS * AC_DEFINE(x) to AC_DEFINE(x,val,"Desc") so that we can get rid of acconfig.h Should I commit this? |
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:46:57
|
Update of /cvsroot/blob/blob/include/blob/proc In directory sc8-pr-cvs1:/tmp/cvs-serv20719/include/blob/proc Modified Files: pxa.h Log Message: Added GPL headers to files I've added and renamed memsetup-pxa250.S to memsetup-pxa.S Index: pxa.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/proc/pxa.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- pxa.h 7 Aug 2003 19:31:00 -0000 1.3 +++ pxa.h 7 Aug 2003 19:46:54 -0000 1.4 @@ -1,7 +1,9 @@ + /* * proc/pxa.h - processor specific defines * * Copyright (C) 2001 Erik Mouw (J.A...@it...) + * Copyright (C) 2003 Abraham van der Merwe <ab...@4d...> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,28 +24,14 @@ #ifndef BLOB_PXA_PROC_H #define BLOB_PXA_PROC_H -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -/* -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p(x) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) - */ - #define io_p2v(x) (x) #define io_v2p(x) (x) #ifndef __ASSEMBLY__ +#define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) - -# define __REG2(x,y) \ +#define __REG2(x,y) \ ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) |
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:46:57
|
Update of /cvsroot/blob/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv20719
Modified Files:
AUTHORS configure.in
Log Message:
Added GPL headers to files I've added and renamed memsetup-pxa250.S to
memsetup-pxa.S
Index: AUTHORS
===================================================================
RCS file: /cvsroot/blob/blob/AUTHORS,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- AUTHORS 6 Aug 2003 22:55:40 -0000 1.13
+++ AUTHORS 7 Aug 2003 19:46:54 -0000 1.14
@@ -91,7 +91,7 @@
===================
- Matej Sekoranja <mat...@co...>
-* CSIR IMS port
-===============
+* CSIR IMS port, PXA processor support
+======================================
- Abraham vd Merwe <ab...@4d...>
Index: configure.in
===================================================================
RCS file: /cvsroot/blob/blob/configure.in,v
retrieving revision 1.64
retrieving revision 1.65
diff -u -d -r1.64 -r1.65
--- configure.in 6 Aug 2003 22:55:40 -0000 1.64
+++ configure.in 7 Aug 2003 19:46:54 -0000 1.65
@@ -407,7 +407,7 @@
pxa250)
dnl PXA250 CPU: SDRAM memory setup code
BLOB_STARTCODE_OBJS="start-pxa.o gpio-pxa.o"
- BLOB_MEMSETUP_OBJS="memsetup-pxa250.o"
+ BLOB_MEMSETUP_OBJS="memsetup-pxa.o"
BLOB_REBOOT_DRIVER_OBJS="reboot-pxa.o"
BLOB_SERIAL_DRIVER_OBJS="serial-pxa.o"
;;
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:46:57
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv20719/src/blob
Modified Files:
gpio-pxa.S
Added Files:
memsetup-pxa.S
Removed Files:
memsetup-pxa250.S
Log Message:
Added GPL headers to files I've added and renamed memsetup-pxa250.S to
memsetup-pxa.S
--- NEW FILE: memsetup-pxa.S ---
/*
* memory-pxa.S - memory setup for PXA architecture
*
* $Id: memsetup-pxa.S,v 1.1 2003/08/07 19:46:54 abz Exp $
*
* Copyright (C) 2003 Abraham van der Merwe <ab...@4d...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
.ident "$Id: memsetup-pxa.S,v 1.1 2003/08/07 19:46:54 abz Exp $"
#ifdef HAVE_CONFIG_H
#include <blob/config.h>
#endif
#include <blob/arch.h>
.text
#define MDCNFG_OFFSET 0x00
#define MDREFR_OFFSET 0x04
#define MSC0_OFFSET 0x08
#define MSC1_OFFSET 0x0c
#define MSC2_OFFSET 0x10
#define MECR_OFFSET 0x14
#define SXLCR_OFFSET 0x18
#define SXCNFG_OFFSET 0x1c
#define SXMRS_OFFSET 0x24
#define MCMEM0_OFFSET 0x28
#define MCMEM1_OFFSET 0x2c
#define MCATT0_OFFSET 0x30
#define MCATT1_OFFSET 0x34
#define MCIO0_OFFSET 0x38
#define MCIO1_OFFSET 0x3c
#define MDMRS_OFFSET 0x40
/*
* The sequence below is based on the recommended init steps detailed
* in the Intel PXA255 Processor Developer's Manual Section 6.11
*/
.macro wait
ldr r2, =OSCR
mov r3, #0
str r3, [r2]
0:
ldr r3, [r2]
cmp r3, #768
bls 0b
.endm
.globl memsetup
memsetup:
/* wait for internal clocks to stabilize */
wait
ldr r1, =0x48000000
/* write MSC0, read back to ensure data latches */
#ifdef MSC0_VALUE
ldr r0, =MSC0_VALUE
str r0, [r1, #MSC0_OFFSET]
ldr r0, [r1, #MSC0_OFFSET]
#endif /* #ifdef MSC0_VALUE */
/* write MSC1, read back to ensure data latches */
#ifdef MSC1_VALUE
ldr r0, =MSC1_VALUE
str r0, [r1, #MSC1_OFFSET]
ldr r0, [r1, #MSC1_OFFSET]
#endif /* #ifdef MSC1_VALUE */
/* write MSC2, read back to ensure data latches */
#ifdef MSC2_VALUE
ldr r0, =MSC2_VALUE
str r0, [r1, #MSC2_OFFSET]
ldr r0, [r1, #MSC2_OFFSET]
#endif /* #ifdef MSC2_VALUE */
/* write MECR */
#ifdef MECR_VALUE
ldr r0, =MECR_VALUE
str r0, [r1, #MECR_OFFSET]
#endif /* #ifdef MECR_VALUE */
/* write MCMEM0 */
#ifdef MCMEM0_VALUE
ldr r0, =MCMEM0_VALUE
str r0, [r1, #MCMEM0_OFFSET]
#endif /* #ifdef MCMEM0_VALUE */
/* write MCMEM1 */
#ifdef MCMEM1_VALUE
ldr r0, =MCMEM1_VALUE
str r0, [r1, #MCMEM1_OFFSET]
#endif /* #ifdef MCMEM1_VALUE */
/* write MCATT0 */
#ifdef MCATT0_VALUE
ldr r0, =MCATT0_VALUE
str r0, [r1, #MCATT0_OFFSET]
#endif /* #ifdef MCATT0_VALUE */
/* write MCATT1 */
#ifdef MCATT1_VALUE
ldr r0, =MCATT1_VALUE
str r0, [r1, #MCATT1_OFFSET]
#endif /* #ifdef MCATT1_VALUE */
/* write MCIO0 */
#ifdef MCIO0_VALUE
ldr r0, =MCIO0_VALUE
str r0, [r1, #MCIO0_OFFSET]
#endif /* #ifdef MCIO0_VALUE */
/* write MCIO1 */
#ifdef MCIO1_VALUE
ldr r0, =MCIO1_VALUE
str r0, [r1, #MCIO1_OFFSET]
#endif /* #ifdef MCIO1_VALUE */
/* get the mdrefr settings (k0run, e0pin, etc.) */
ldr r3, =MDREFR_VALUE
/* extract DRI field (we need a valid DRI field) */
ldr r2, =0xfff
and r3, r3, r2
/* get the reset state of MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
/* clear the DRI field */
bic r4, r4, r2
/* insert the valid DRI field loaded above */
orr r4, r4, r3
/* write back MDREFR */
str r4, [r1, #MDREFR_OFFSET]
/*
* I am hard-coding in 50/100/300 clock speeds for now.
* This needs testing since I hacked up a large, ugly version
* of this that was Lubbock-specific. -Rusty
*/
/* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
/* set K1RUN if bank 0 installed */
orr r4, r4, #0x00010000
/* set K1DB2 (SDClk[1] = MemClk/2) */
orreq r4, r4, #0x00020000
/* write back MDREFR */
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
/* deassert SLFRSH */
bic r4, r4, #0x00400000
/* write back MDREFR */
str r4, [r1, #MDREFR_OFFSET]
/* assert E1PIN */
orr r4, r4, #0x00008000
/* write back MDREFR */
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
.rept 3
nop
.endr
/* fetch platform value of MDCNFG */
ldr r2, =MDCNFG_VALUE
/* disable all sdram banks */
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
/* write initial value of MDCNFG, w/o enabling sdram banks */
str r2, [r1, #MDCNFG_OFFSET]
/* wait for internal clocks to stabilize */
wait
/* turn everything off (caches off, MMU off, etc.) */
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0
/*
* Access memory *not yet enabled* for CBR refresh cycles (8)
* CBR is generated for all banks
*/
ldr r2, =PXA_SDRAM_BANK0
.rept 8
str r2, [r2]
.endr
/* fetch current MDCNFG value */
ldr r3, [r1, #MDCNFG_OFFSET]
/* enable sdram bank 0 if installed (must do for any populated bank) */
orr r3, r3, #MDCNFG_DE0
/* write back mdcnfg, enabling the sdram bank(s) */
str r3, [r1, #MDCNFG_OFFSET]
/* write MDMRS */
ldr r2, =MDMRS_VALUE
str r2, [r1, #MDMRS_OFFSET]
mov pc, lr
Index: gpio-pxa.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/gpio-pxa.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- gpio-pxa.S 7 Aug 2003 19:31:00 -0000 1.2
+++ gpio-pxa.S 7 Aug 2003 19:46:54 -0000 1.3
@@ -1,11 +1,27 @@
/*
- * gpio-pxa.S - Part of the AVO Architecture Boot Loader
+ * gpio-pxa.S - gpio setup for PXA architecture
*
- * Written by Abraham van der Merwe <ab...@bl...>
- * Copyright (c) 2002, 2003 Blio Corporation (Pty) Ltd.
- * All Rights Reserved.
+ * $Id$
+ *
+ * Copyright (C) 2003 Abraham van der Merwe <ab...@4d...>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+
+.ident "$Id$"
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
--- memsetup-pxa250.S DELETED ---
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:31:06
|
Update of /cvsroot/blob/blob/src/lib
In directory sc8-pr-cvs1:/tmp/cvs-serv17234/src/lib
Modified Files:
command.c
Log Message:
Fixed a couple of bugs in my previous set of changes. The PXA port is now
fully functional. Also added a patch from Yves Rutschle which fixes a bug in
the serial code.
Index: command.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/command.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- command.c 13 Feb 2002 00:10:57 -0000 1.12
+++ command.c 7 Aug 2003 19:31:01 -0000 1.13
@@ -275,7 +275,7 @@
for(numRead = 0, i = 0; numRead < maxRead;) {
/* try to get a byte from the serial port */
- while(serial_poll() != 0) {
+ while(serial_poll() == 0) {
currentTime = TimerGetTime();
/* check timeout value */
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:31:06
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv17234/src/blob
Modified Files:
csir_ims.c gpio-pxa.S lart.c main.c partition.c start-pxa.S
start-sa11x0.S
Log Message:
Fixed a couple of bugs in my previous set of changes. The PXA port is now
fully functional. Also added a patch from Yves Rutschle which fixes a bug in
the serial code.
Index: csir_ims.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/csir_ims.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- csir_ims.c 6 Aug 2003 23:00:52 -0000 1.1
+++ csir_ims.c 7 Aug 2003 19:31:00 -0000 1.2
@@ -37,6 +37,7 @@
#include <blob/command.h>
#include <blob/uucodec.h>
#include <blob/led.h>
+#include <blob/partition.h>
#define GPIO25_LED GPIO_bit(25)
@@ -77,16 +78,15 @@
led_locked = 0;
}
-static led_driver_t csir_ims_led_driver = {
- .led_on = csir_ims_led_on,
- .led_off = csir_ims_led_off,
- .led_toggle = csir_ims_led_toggle,
- .led_lock = csir_ims_led_lock,
- .led_unlock = csir_ims_led_unlock
-};
-
static void csir_ims_init_driver (void)
{
+ static led_driver_t csir_ims_led_driver = {
+ .led_on = csir_ims_led_on,
+ .led_off = csir_ims_led_off,
+ .led_toggle = csir_ims_led_toggle,
+ .led_lock = csir_ims_led_lock,
+ .led_unlock = csir_ims_led_unlock
+ };
static const flash_descriptor_t flash[] = {
{
.size = 128 * 1024,
@@ -95,6 +95,54 @@
},
{ /* NULL block */ }
};
+ static blob_partition_t partitions[] = {
+ {
+ .magic = BLOB_DEFAULT_PART_TABLE_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = 0x00000000,
+ .size = BLOB_PART_SIZ_FULL
+ }, {
+ .magic = BLOB_PART_VALID_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = BLOB_PART_OFS_APPEND,
+ .size = BLOB_FLASH_LEN,
+ .name = "blob",
+ .mem_base = BLOB_RAM_BASE
+ }, {
+ .magic = BLOB_PART_VALID_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = BLOB_PART_OFS_APPEND,
+ .size = PARAM_FLASH_LEN,
+ .name = "param",
+ .flags = BLOB_PART_FLAG_PTABLE
+ }, {
+ .magic = BLOB_PART_VALID_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = BLOB_PART_OFS_APPEND,
+ .size = KERNEL_FLASH_LEN,
+ .name = "kernel",
+ .flags = BLOB_PART_FLAG_EXEC,
+ .mem_base = KERNEL_RAM_BASE,
+ .entry_point= KERNEL_RAM_BASE
+ }, {
+ .magic = BLOB_PART_VALID_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = BLOB_PART_OFS_APPEND,
+ .size = RAMDISK_FLASH_LEN,
+ .name = "ramdisk",
+ .flags = BLOB_PART_FLAG_LOAD,
+ .mem_base = RAMDISK_RAM_BASE
+ }, {
+ .magic = BLOB_PART_VALID_MAGIC,
+ .next = sizeof (blob_partition_t),
+ .offset = BLOB_PART_OFS_APPEND,
+ .size = BLOB_PART_SIZ_FULL,
+ .name = "jffs2",
+ .flags = BLOB_PART_FLAG_JFFS2
+ }, {
+ .magic = BLOB_PART_LAST_MAGIC
+ }
+ };
GPDR0 |= GPIO25_LED;
@@ -104,6 +152,9 @@
serial_driver = &pxa_serial_driver;
flash_driver = &intel16_flash_driver;
led_driver = &csir_ims_led_driver;
+
+ default_partition_table = partitions;
+ flash_partition_table = (blob_partition_t *) 0x00000000;
}
__initlist (csir_ims_init_driver,INIT_LEVEL_DRIVER_SELECTION);
Index: gpio-pxa.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/gpio-pxa.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- gpio-pxa.S 6 Aug 2003 23:00:52 -0000 1.1
+++ gpio-pxa.S 7 Aug 2003 19:31:00 -0000 1.2
@@ -8,41 +8,52 @@
*/
#ifdef HAVE_CONFIG_H
-#include <blob/config.h>
+# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
-REG_BASE:
- .word GPDR0, GPDR1, GPDR2
- .word GPSR0, GPSR1, GPSR2
- .word GPCR0, GPCR1, GPCR2
- .word GAFR0_L, GAFR1_L, GAFR2_L
- .word GAFR0_U, GAFR1_U, GAFR2_U
-
-VALUE_BASE:
- .word GPDR0_VALUE, GPDR1_VALUE, GPDR2_VALUE
- .word GPSR0_VALUE, GPSR1_VALUE, GPSR2_VALUE
- .word GPCR0_VALUE, GPCR1_VALUE, GPCR2_VALUE
- .word GAFR0_L_VALUE, GAFR1_L_VALUE, GAFR2_L_VALUE
- .word GAFR0_U_VALUE, GAFR1_U_VALUE, GAFR2_U_VALUE
+.macro save, reg, value
+ ldr r1, =\reg
+ ldr r0, =\value
+ str r0, [r1]
+.endm
.globl gpiosetup
-.type gpiosetup, #function
gpiosetup:
- ldr r1, REG_BASE
- ldr r0, VALUE_BASE
- mov r2, r0
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r1, r2
- blo 0b
+ save GPSR0, GPSR0_VALUE
+ save GPSR1, GPSR1_VALUE
+ save GPSR2, GPSR2_VALUE
+
+ save GPCR0, GPCR0_VALUE
+ save GPCR1, GPCR1_VALUE
+ save GPCR2, GPCR2_VALUE
+
+#if 0
+ save GRER0, GRER0_VALUE
+ save GRER1, GRER1_VALUE
+ save GRER2, GRER2_VALUE
+
+ save GFER0, GFER0_VALUE
+ save GFER1, GFER1_VALUE
+ save GFER2, GFER2_VALUE
+#endif
+
+ save GPDR0, GPDR0_VALUE
+ save GPDR1, GPDR1_VALUE
+ save GPDR2, GPDR2_VALUE
+
+ save GAFR0_L, GAFR0_L_VALUE
+ save GAFR0_U, GAFR0_U_VALUE
+ save GAFR1_L, GAFR1_L_VALUE
+ save GAFR1_U, GAFR1_U_VALUE
+ save GAFR2_L, GAFR2_L_VALUE
+ save GAFR2_U, GAFR2_U_VALUE
ldr r1, =PSSR
- mov r0, #(PSSR_RDH | PSSR_PH)
+ mov r0, #PSSR_RDH
str r0, [r1]
mov pc, lr
Index: lart.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/lart.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- lart.c 13 Feb 2003 01:10:53 -0000 1.9
+++ lart.c 7 Aug 2003 19:31:00 -0000 1.10
@@ -80,7 +80,7 @@
next: sizeof(blob_partition_t),
offset: PARAM_FLASH_BASE,
size: PARAM_FLASH_LEN,
- name: "parameters",
+ name: "param",
flags: BLOB_PART_FLAG_PTABLE
},
{
Index: main.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/main.c,v
retrieving revision 1.52
retrieving revision 1.53
diff -u -d -r1.52 -r1.53
--- main.c 28 Jan 2003 03:36:36 -0000 1.52
+++ main.c 7 Aug 2003 19:31:00 -0000 1.53
@@ -692,7 +692,8 @@
static void *find_parameters(void)
{
- const blob_partition_t *p = pt_find_by_name("parameters");
+ const blob_partition_t *p = pt_find_by_name("param");
- return p ? pt_flash_start(p) : 0;
+ return p ? pt_flash_start(p) : NULL;
}
+
Index: partition.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/partition.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- partition.c 28 Jan 2003 03:38:48 -0000 1.9
+++ partition.c 7 Aug 2003 19:31:01 -0000 1.10
@@ -219,7 +219,7 @@
t->size, t->offset, t->size, t->name);
if(t->flags & BLOB_PART_FLAG_PTABLE)
- printf(" contains partition table\n");
+ printf(" contains parameter blocks\n");
if(t->mem_base)
printf(" %sload at 0x%08x\n",
Index: start-pxa.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-pxa.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- start-pxa.S 6 Aug 2003 22:55:41 -0000 1.2
+++ start-pxa.S 7 Aug 2003 19:31:01 -0000 1.3
@@ -49,6 +49,7 @@
str r1, [r0]
real_reset:
+ bl gpiosetup
bl ledsetup
bl memsetup
bl normal_boot
Index: start-sa11x0.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-sa11x0.S,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- start-sa11x0.S 6 Aug 2003 22:55:41 -0000 1.6
+++ start-sa11x0.S 7 Aug 2003 19:31:01 -0000 1.7
@@ -120,9 +120,6 @@
real_reset:
- /* init GPIOs */
- bl gpiosetup
-
/* init LED */
bl ledinit
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:31:06
|
Update of /cvsroot/blob/blob/include/blob/arch In directory sc8-pr-cvs1:/tmp/cvs-serv17234/include/blob/arch Modified Files: csir_ims.h Log Message: Fixed a couple of bugs in my previous set of changes. The PXA port is now fully functional. Also added a patch from Yves Rutschle which fixes a bug in the serial code. Index: csir_ims.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch/csir_ims.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- csir_ims.h 6 Aug 2003 23:00:52 -0000 1.1 +++ csir_ims.h 7 Aug 2003 19:30:59 -0000 1.2 @@ -47,6 +47,10 @@ #define RAMDISK_FLASH_BASE (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN) #define RAMDISK_FLASH_LEN (4 * 1024 * 1024) +/* this needs to be defined if you want parameter block support */ +#define PARAM_START PARAM_FLASH_BASE +#define PARAM_LEN PARAM_FLASH_LEN + /* load ramdisk into ram */ #define LOAD_RAMDISK 1 @@ -70,21 +74,19 @@ #define MDCNFG_VALUE 0x000019c9 #define MDMRS_VALUE 0x00020002 -#define _U(x) GPIO_INPUT - /* GPIO configuration */ -#define GPIO0_VALUE _U(GPIO_OUT_LO) -#define GPIO1_VALUE _U(GPIO_OUT_LO) -#define GPIO2_VALUE _U(GPIO_OUT_LO) +#define GPIO0_VALUE GPIO_OUT_LO +#define GPIO1_VALUE GPIO_OUT_LO +#define GPIO2_VALUE GPIO_OUT_LO #define GPIO3_VALUE GPIO_INPUT /* eth_wakeup */ #define GPIO4_VALUE GPIO_INPUT /* bank_switch_int */ #define GPIO5_VALUE GPIO_INPUT /* eth_link_status */ -#define GPIO6_VALUE _U(GPIO_OUT_LO) +#define GPIO6_VALUE GPIO_OUT_LO #define GPIO7_VALUE GPIO_OUT_LO /* cpld_clk */ -#define GPIO8_VALUE _U(GPIO_OUT_LO) +#define GPIO8_VALUE GPIO_OUT_LO #define GPIO9_VALUE GPIO_INPUT /* eth_int */ #define GPIO10_VALUE GPIO_OUT_HI /* eth_reset */ -#define GPIO11_VALUE _U(GPIO_OUT_LO) +#define GPIO11_VALUE GPIO_OUT_LO #define GPIO12_VALUE GPIO_OUT_LO /* watchdog_strobe */ #define GPIO13_VALUE GPIO_INPUT /* cpld_hw_reset */ #define GPIO14_VALUE GPIO_INPUT /* cpld_?? */ @@ -92,71 +94,71 @@ #define GPIO16_VALUE GPIO_OUT_LO #define GPIO17_VALUE GPIO_INPUT /* cpld_?? */ #define GPIO18_VALUE GPIO_INPUT /* vlio_ready_signal */ -#define GPIO19_VALUE _U(GPIO_OUT_LO) -#define GPIO20_VALUE _U(GPIO_OUT_LO) -#define GPIO21_VALUE _U(GPIO_OUT_LO) -#define GPIO22_VALUE _U(GPIO_OUT_LO) -#define GPIO23_VALUE _U(GPIO_OUT_LO) -#define GPIO24_VALUE _U(GPIO_OUT_LO) +#define GPIO19_VALUE GPIO_OUT_LO +#define GPIO20_VALUE GPIO_OUT_LO +#define GPIO21_VALUE GPIO_OUT_LO +#define GPIO22_VALUE GPIO_OUT_LO +#define GPIO23_VALUE GPIO_OUT_LO +#define GPIO24_VALUE GPIO_OUT_LO #define GPIO25_VALUE GPIO_OUT_HI /* LED [debug] */ -#define GPIO26_VALUE _U(GPIO_OUT_LO) -#define GPIO27_VALUE _U(GPIO_OUT_LO) -#define GPIO28_VALUE _U(GPIO_OUT_LO) -#define GPIO29_VALUE _U(GPIO_OUT_LO) -#define GPIO30_VALUE _U(GPIO_OUT_LO) -#define GPIO31_VALUE _U(GPIO_OUT_LO) -#define GPIO32_VALUE _U(GPIO_OUT_LO) +#define GPIO26_VALUE GPIO_OUT_LO +#define GPIO27_VALUE GPIO_OUT_LO +#define GPIO28_VALUE GPIO_OUT_LO +#define GPIO29_VALUE GPIO_OUT_LO +#define GPIO30_VALUE GPIO_OUT_LO +#define GPIO31_VALUE GPIO_OUT_LO +#define GPIO32_VALUE GPIO_OUT_LO #define GPIO33_VALUE GPIO_OUT_HI /* nCS5 [unused] */ #define GPIO34_VALUE (GPIO_INPUT | GPIO_ALT_FN1) /* FFRXD */ -#define GPIO35_VALUE _U(GPIO_OUT_LO) -#define GPIO36_VALUE _U(GPIO_OUT_LO) -#define GPIO37_VALUE _U(GPIO_OUT_LO) -#define GPIO38_VALUE _U(GPIO_OUT_LO) +#define GPIO35_VALUE GPIO_OUT_LO +#define GPIO36_VALUE GPIO_OUT_LO +#define GPIO37_VALUE GPIO_OUT_LO +#define GPIO38_VALUE GPIO_OUT_LO #define GPIO39_VALUE (GPIO_OUT_LO | GPIO_ALT_FN2) /* FFTXD */ -#define GPIO40_VALUE _U(GPIO_OUT_LO) -#define GPIO41_VALUE _U(GPIO_OUT_LO) -#define GPIO42_VALUE _U(GPIO_OUT_LO) -#define GPIO43_VALUE _U(GPIO_OUT_LO) -#define GPIO44_VALUE _U(GPIO_OUT_LO) -#define GPIO45_VALUE _U(GPIO_OUT_LO) -#define GPIO46_VALUE _U(GPIO_OUT_LO) -#define GPIO47_VALUE _U(GPIO_OUT_LO) -#define GPIO48_VALUE _U(GPIO_OUT_LO) +#define GPIO40_VALUE GPIO_OUT_LO +#define GPIO41_VALUE GPIO_OUT_LO +#define GPIO42_VALUE GPIO_OUT_LO +#define GPIO43_VALUE GPIO_OUT_LO +#define GPIO44_VALUE GPIO_OUT_LO +#define GPIO45_VALUE GPIO_OUT_LO +#define GPIO46_VALUE GPIO_OUT_LO +#define GPIO47_VALUE GPIO_OUT_LO +#define GPIO48_VALUE GPIO_OUT_LO #define GPIO49_VALUE GPIO_OUT_HI /* cpld_pcmcia_pwe */ -#define GPIO50_VALUE _U(GPIO_OUT_LO) -#define GPIO51_VALUE _U(GPIO_OUT_LO) -#define GPIO52_VALUE _U(GPIO_OUT_LO) -#define GPIO53_VALUE _U(GPIO_OUT_LO) -#define GPIO54_VALUE _U(GPIO_OUT_LO) -#define GPIO55_VALUE _U(GPIO_OUT_LO) +#define GPIO50_VALUE GPIO_OUT_LO +#define GPIO51_VALUE GPIO_OUT_LO +#define GPIO52_VALUE GPIO_OUT_LO +#define GPIO53_VALUE GPIO_OUT_LO +#define GPIO54_VALUE GPIO_OUT_LO +#define GPIO55_VALUE GPIO_OUT_LO #define GPIO56_VALUE GPIO_INPUT #define GPIO57_VALUE GPIO_INPUT -#define GPIO58_VALUE _U(GPIO_OUT_LO) -#define GPIO59_VALUE _U(GPIO_OUT_LO) -#define GPIO60_VALUE _U(GPIO_OUT_LO) -#define GPIO61_VALUE _U(GPIO_OUT_LO) -#define GPIO62_VALUE _U(GPIO_OUT_LO) -#define GPIO63_VALUE _U(GPIO_OUT_LO) -#define GPIO64_VALUE _U(GPIO_OUT_LO) -#define GPIO65_VALUE _U(GPIO_OUT_LO) -#define GPIO66_VALUE _U(GPIO_OUT_LO) -#define GPIO67_VALUE _U(GPIO_OUT_LO) -#define GPIO68_VALUE _U(GPIO_OUT_LO) -#define GPIO69_VALUE _U(GPIO_OUT_LO) -#define GPIO70_VALUE _U(GPIO_OUT_LO) -#define GPIO71_VALUE _U(GPIO_OUT_LO) -#define GPIO72_VALUE _U(GPIO_OUT_LO) -#define GPIO73_VALUE _U(GPIO_OUT_LO) -#define GPIO74_VALUE _U(GPIO_OUT_LO) -#define GPIO75_VALUE _U(GPIO_OUT_LO) -#define GPIO76_VALUE _U(GPIO_OUT_LO) -#define GPIO77_VALUE _U(GPIO_OUT_LO) +#define GPIO58_VALUE GPIO_OUT_LO +#define GPIO59_VALUE GPIO_OUT_LO +#define GPIO60_VALUE GPIO_OUT_LO +#define GPIO61_VALUE GPIO_OUT_LO +#define GPIO62_VALUE GPIO_OUT_LO +#define GPIO63_VALUE GPIO_OUT_LO +#define GPIO64_VALUE GPIO_OUT_LO +#define GPIO65_VALUE GPIO_OUT_LO +#define GPIO66_VALUE GPIO_OUT_LO +#define GPIO67_VALUE GPIO_OUT_LO +#define GPIO68_VALUE GPIO_OUT_LO +#define GPIO69_VALUE GPIO_OUT_LO +#define GPIO70_VALUE GPIO_OUT_LO +#define GPIO71_VALUE GPIO_OUT_LO +#define GPIO72_VALUE GPIO_OUT_LO +#define GPIO73_VALUE GPIO_OUT_LO +#define GPIO74_VALUE GPIO_OUT_LO +#define GPIO75_VALUE GPIO_OUT_LO +#define GPIO76_VALUE GPIO_OUT_LO +#define GPIO77_VALUE GPIO_OUT_LO #define GPIO78_VALUE (GPIO_OUT_HI | GPIO_ALT_FN2) /* nCS2 [img_buffer] */ #define GPIO79_VALUE (GPIO_OUT_HI | GPIO_ALT_FN2) /* nCS3 [eth] */ #define GPIO80_VALUE GPIO_OUT_HI /* nCS4 [unused] */ -#define GPIO81_VALUE _U(GPIO_OUT_LO) -#define GPIO82_VALUE _U(GPIO_OUT_LO) -#define GPIO83_VALUE _U(GPIO_OUT_LO) -#define GPIO84_VALUE _U(GPIO_OUT_LO) +#define GPIO81_VALUE GPIO_OUT_LO +#define GPIO82_VALUE GPIO_OUT_LO +#define GPIO83_VALUE GPIO_OUT_LO +#define GPIO84_VALUE GPIO_OUT_LO #endif /* #ifndef BLOB_ARCH_CSIR_IMS_H */ |
|
From: Abraham vd M. <ab...@us...> - 2003-08-07 19:31:06
|
Update of /cvsroot/blob/blob/include/blob/proc In directory sc8-pr-cvs1:/tmp/cvs-serv17234/include/blob/proc Modified Files: pxa.h Log Message: Fixed a couple of bugs in my previous set of changes. The PXA port is now fully functional. Also added a patch from Yves Rutschle which fixes a bug in the serial code. Index: pxa.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/proc/pxa.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- pxa.h 6 Aug 2003 22:55:40 -0000 1.2 +++ pxa.h 7 Aug 2003 19:31:00 -0000 1.3 @@ -179,7 +179,7 @@ ) #define _FB(x) ((x) & GPIO_ALT_FN_MASK) -#define _FM(x) (_FB(GPIO##x##_VALUE) << ((x) & 0x0f)) +#define _FM(x) (_FB(GPIO##x##_VALUE) << (((x) & 0x0f) << 1)) #define GAFR0_L_VALUE ( \ _FM(0) | _FM(1) | _FM(2) | _FM(3) | \ |
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 23:00:55
|
Update of /cvsroot/blob/blob/src/diag
In directory sc8-pr-cvs1:/tmp/cvs-serv9035/src/diag
Added Files:
csir_ims.c
Log Message:
Added new files, removed old stale files
--- NEW FILE: csir_ims.c ---
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/types.h>
#include <blob/errno.h>
#include <blob/util.h>
#include <blob/command.h>
#include <blob/init.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/arch.h>
static void csir_ims_init_hardware(void)
{
serial_driver = &pxa_serial_driver;
}
__initlist(csir_ims_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 23:00:55
|
Update of /cvsroot/blob/blob/include/blob/proc
In directory sc8-pr-cvs1:/tmp/cvs-serv9035/include/blob/proc
Added Files:
Makefile.am sa1100.h sa1111.h
Removed Files:
sa11x0.h
Log Message:
Added new files, removed old stale files
--- NEW FILE: Makefile.am ---
# -*- makefile -*-
###########################################################################
## Filename: Makefile.am
## Version: $Id: Makefile.am,v 1.1 2003/08/06 23:00:52 abz Exp $
## Copyright: Copyright (C) 1999, Erik Mouw
## Author: Erik Mouw <J.A...@it...>
## Description: Makefile
## Created at: Tue Aug 17 17:25:56 1999
## Modified by: Erik Mouw <J.A...@it...>
## Modified at: Tue Sep 28 23:36:51 1999
###########################################################################
noinst_HEADERS = \
pxa.h \
sa1100.h \
sa1111.h
CLEANFILES = ${srcdir}/*~
--- NEW FILE: sa1100.h ---
/*
* proc/sa11x0.h - processor specific defines
*
* Copyright (C) 2001 Erik Mouw (J.A...@it...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef BLOB_SA11X0_PROC_H
#define BLOB_SA11X0_PROC_H
/* memory start and end */
#define MEMORY_START (0xc0000000)
#define MEMORY_END (0xe0000000)
/*
* CPU frequency table.
*
* See Section 8.2 (Core Clock Configuration Register) SA-1110 Developers
* Manual for more information.
*
* f_cpu = 16*f_osc + n*4*f_osc
* = 4*(n+4)*f_osc
*
* We have 3.6864-MHz oscillator.
*
* CCF[4:0] 3.6864-MHz Crystal Oscillator 3.5795-MHz Crystal Oscillator
* -------------------------------------------------------------------------
* 00 59.0 57.3
* 01 73.7 71.6
* 02 88.5 85.9
* 03 103.2 100.2
* 04 118.0 114.5
* 05 132.7 128.9
* 06 147.5 143.2
* 07 162.2 157.5
* 08 176.9 171.8
* 09 191.7 186.1
* 0a 206.4 200.5
* 0b 221.2 214.8
*
* these are undocumented.
*
* 0c 235.9 ??
* 0d 250.7 ??
* 0e 265.4 ??
* 0f 280.2 ??
*/
#define CPU_CORE_SPEED_59mhz 0x00
#define CPU_CORE_SPEED_73mhz 0x01
#define CPU_CORE_SPEED_88mhz 0x02
#define CPU_CORE_SPEED_103mhz 0x03
#define CPU_CORE_SPEED_118mhz 0x04
#define CPU_CORE_SPEED_132mhz 0x05
#define CPU_CORE_SPEED_147mhz 0x06
#define CPU_CORE_SPEED_162mhz 0x07
#define CPU_CORE_SPEED_176mhz 0x08
#define CPU_CORE_SPEED_191mhz 0x09
#define CPU_CORE_SPEED_206mhz 0x0a
#define CPU_CORE_SPEED_221mhz 0x0b
#define CPU_CORE_SPEED_235mhz 0x0c
#define CPU_CORE_SPEED_250mhz 0x0d
#define CPU_CORE_SPEED_265mhz 0x0e
#define CPU_CORE_SPEED_280mhz 0x0f
#define io_p2v(x) (x)
#define __REG(x) (*((volatile u32 *)io_p2v(x)))
/* Tell SA-1100.h to shut up; we're including it anyway. Nyah nyah ;-) */
#define __ASM_ARCH_HARDWARE_H
#include <asm-arm/arch-sa1100/SA-1100.h>
#endif
--- NEW FILE: sa1111.h ---
/*
* sa1111.h: Defines and macros for accessing the SA1111. Created from
* the kernel source.
*
* Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
*
* $Id: sa1111.h,v 1.1 2003/08/06 23:00:52 abz Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ident "$Id: sa1111.h,v 1.1 2003/08/06 23:00:52 abz Exp $"
#ifndef BLOB_SA1111_H
#define BLOB_SA1111_H
#include <blob/arch.h>
#include <blob/bitfield.h>
#define SA1111_VBASE 0x40000000
/*
* 26 bits of the SA-1110 address bus are available to the SA-1111.
* Use these when feeding target addresses to the DMA engines.
*/
#define MEM_REG(adr) (*((u32 *)(adr)))
#define SA1111_ADDR_WIDTH (26)
#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
/*
* Don't ask the (SAC) DMA engines to move less than this amount.
*/
#define SA1111_SAC_DMA_MIN_XFER (0x800)
/*
* SA1111 register definitions.
*/
#define SA1111_REG(x) MEM_REG(SA1111_VBASE + (x))
/* System Bus Interface (SBI)
*
* Registers
* SKCR Control Register
* SMCR Shared Memory Controller Register
* SKID ID Register
*/
#define SA1111_SKCR 0x0000
#define SA1111_SMCR 0x0004
#define SA1111_SKID 0x0008
#define SBI_SKCR SA1111_REG(SA1111_SKCR)
#define SBI_SMCR SA1111_REG(SA1111_SMCR)
#define SBI_SKID SA1111_REG(SA1111_SKID)
#define SKCR_PLL_BYPASS (1<<0)
#define SKCR_RCLKEN (1<<1)
#define SKCR_SLEEP (1<<2)
#define SKCR_DOZE (1<<3)
#define SKCR_VCO_OFF (1<<4)
#define SKCR_SCANTSTEN (1<<5)
#define SKCR_CLKTSTEN (1<<6)
#define SKCR_RDYEN (1<<7)
#define SKCR_SELAC (1<<8)
#define SKCR_OPPC (1<<9)
#define SKCR_PLLTSTEN (1<<10)
#define SKCR_USBIOTSTEN (1<<11)
/*
* Don't believe the specs! Take them, throw them outside. Leave them
* there for a week. Spit on them. Walk on them. Stamp on them.
* Pour gasoline over them and finally burn them. Now think about coding.
* - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
* - The Feb 2001 errata (278260-010) says that the previous errata
* (278260-009) is wrong, and its bit actually 12, fixed in spec
* 278242-003.
* - The SA1111 manual (278242) says bit 12, but 0 to enable.
* - Reality is bit 13, 1 to enable.
* -- rmk
*/
#define SKCR_OE_EN (1<<13)
#define SMCR_DTIM (1<<0)
#define SMCR_MBGE (1<<1)
#define SMCR_DRAC_0 (1<<2)
#define SMCR_DRAC_1 (1<<3)
#define SMCR_DRAC_2 (1<<4)
#define SMCR_DRAC Fld(3, 2)
#define SMCR_CLAT (1<<5)
#define SKID_SIREV_MASK (0x000000f0)
#define SKID_MTREV_MASK (0x0000000f)
#define SKID_ID_MASK (0xffffff00)
#define SKID_SA1111_ID (0x690cc200)
/*
* System Controller
*
* Registers
* SKPCR Power Control Register
* SKCDR Clock Divider Register
* SKAUD Audio Clock Divider Register
* SKPMC PS/2 Mouse Clock Divider Register
* SKPTC PS/2 Track Pad Clock Divider Register
* SKPEN0 PWM0 Enable Register
* SKPWM0 PWM0 Clock Register
* SKPEN1 PWM1 Enable Register
* SKPWM1 PWM1 Clock Register
*/
#define SKPCR SA1111_REG(0x0200)
#define SKCDR SA1111_REG(0x0204)
#define SKAUD SA1111_REG(0x0208)
#define SKPMC SA1111_REG(0x020c)
#define SKPTC SA1111_REG(0x0210)
#define SKPEN0 SA1111_REG(0x0214)
#define SKPWM0 SA1111_REG(0x0218)
#define SKPEN1 SA1111_REG(0x021c)
#define SKPWM1 SA1111_REG(0x0220)
#define SKPCR_UCLKEN (1<<0)
#define SKPCR_ACCLKEN (1<<1)
#define SKPCR_I2SCLKEN (1<<2)
#define SKPCR_L3CLKEN (1<<3)
#define SKPCR_SCLKEN (1<<4)
#define SKPCR_PMCLKEN (1<<5)
#define SKPCR_PTCLKEN (1<<6)
#define SKPCR_DCLKEN (1<<7)
#define SKPCR_PWMCLKEN (1<<8)
/*
* USB Host controller
*/
#define USB_OHCI_OP_BASE SA1111_REG(0x0400)
#define USB_STATUS SA1111_REG(0x0518)
#define USB_RESET SA1111_REG(0x051c)
#define USB_INTERRUPTEST SA1111_REG(0x0520)
#define USB_RESET_FORCEIFRESET (1 << 0)
#define USB_RESET_FORCEHCRESET (1 << 1)
#define USB_RESET_CLKGENRESET (1 << 2)
#define USB_RESET_SIMSCALEDOWN (1 << 3)
#define USB_RESET_USBINTTEST (1 << 4)
#define USB_RESET_SLEEPSTBYEN (1 << 5)
#define USB_RESET_PWRSENSELOW (1 << 6)
#define USB_RESET_PWRCTRLLOW (1 << 7)
/*
* Serial Audio Controller
*
* Registers
* SACR0 Serial Audio Common Control Register
* SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
* SACR2 Serial Audio AC-link Control Register
* SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
* SASR1 Serial Audio AC-link Interface & FIFO Status Register
* SASCR Serial Audio Status Clear Register
* L3_CAR L3 Control Bus Address Register
* L3_CDR L3 Control Bus Data Register
* ACCAR AC-link Command Address Register
* ACCDR AC-link Command Data Register
* ACSAR AC-link Status Address Register
* ACSDR AC-link Status Data Register
* SADTCS Serial Audio DMA Transmit Control/Status Register
* SADTSA Serial Audio DMA Transmit Buffer Start Address A
* SADTCA Serial Audio DMA Transmit Buffer Count Register A
* SADTSB Serial Audio DMA Transmit Buffer Start Address B
* SADTCB Serial Audio DMA Transmit Buffer Count Register B
* SADRCS Serial Audio DMA Receive Control/Status Register
* SADRSA Serial Audio DMA Receive Buffer Start Address A
* SADRCA Serial Audio DMA Receive Buffer Count Register A
* SADRSB Serial Audio DMA Receive Buffer Start Address B
* SADRCB Serial Audio DMA Receive Buffer Count Register B
* SAITR Serial Audio Interrupt Test Register
* SADR Serial Audio Data Register (16 x 32-bit)
*/
#define SACR0 SA1111_REG(0x0600)
#define SACR1 SA1111_REG(0x0604)
#define SACR2 SA1111_REG(0x0608)
#define SASR0 SA1111_REG(0x060c)
#define SASR1 SA1111_REG(0x0610)
#define SASCR SA1111_REG(0x0618)
#define L3_CAR SA1111_REG(0x061c)
#define L3_CDR SA1111_REG(0x0620)
#define ACCAR SA1111_REG(0x0624)
#define ACCDR SA1111_REG(0x0628)
#define ACSAR SA1111_REG(0x062c)
#define ACSDR SA1111_REG(0x0630)
#define SADTCS SA1111_REG(0x0634)
#define SADTSA SA1111_REG(0x0638)
#define SADTCA SA1111_REG(0x063c)
#define SADTSB SA1111_REG(0x0640)
#define SADTCB SA1111_REG(0x0644)
#define SADRCS SA1111_REG(0x0648)
#define SADRSA SA1111_REG(0x064c)
#define SADRCA SA1111_REG(0x0650)
#define SADRSB SA1111_REG(0x0654)
#define SADRCB SA1111_REG(0x0658)
#define SAITR SA1111_REG(0x065c)
#define SADR SA1111_REG(0x0680)
#define SACR0_ENB (1<<0)
#define SACR0_BCKD (1<<2)
#define SACR0_RST (1<<3)
#define SACR1_AMSL (1<<0)
#define SACR1_L3EN (1<<1)
#define SACR1_L3MB (1<<2)
#define SACR1_DREC (1<<3)
#define SACR1_DRPL (1<<4)
#define SACR1_ENLBF (1<<5)
#define SACR2_TS3V (1<<0)
#define SACR2_TS4V (1<<1)
#define SACR2_WKUP (1<<2)
#define SACR2_DREC (1<<3)
#define SACR2_DRPL (1<<4)
#define SACR2_ENLBF (1<<5)
#define SACR2_RESET (1<<6)
#define SASR0_TNF (1<<0)
#define SASR0_RNE (1<<1)
#define SASR0_BSY (1<<2)
#define SASR0_TFS (1<<3)
#define SASR0_RFS (1<<4)
#define SASR0_TUR (1<<5)
#define SASR0_ROR (1<<6)
#define SASR0_L3WD (1<<16)
#define SASR0_L3RD (1<<17)
#define SASR1_TNF (1<<0)
#define SASR1_RNE (1<<1)
#define SASR1_BSY (1<<2)
#define SASR1_TFS (1<<3)
#define SASR1_RFS (1<<4)
#define SASR1_TUR (1<<5)
#define SASR1_ROR (1<<6)
#define SASR1_CADT (1<<16)
#define SASR1_SADR (1<<17)
#define SASR1_RSTO (1<<18)
#define SASR1_CLPM (1<<19)
#define SASR1_CRDY (1<<20)
#define SASR1_RS3V (1<<21)
#define SASR1_RS4V (1<<22)
#define SASCR_TUR (1<<5)
#define SASCR_ROR (1<<6)
#define SASCR_DTS (1<<16)
#define SASCR_RDD (1<<17)
#define SASCR_STO (1<<18)
#define SADTCS_TDEN (1<<0)
#define SADTCS_TDIE (1<<1)
#define SADTCS_TDBDA (1<<3)
#define SADTCS_TDSTA (1<<4)
#define SADTCS_TDBDB (1<<5)
#define SADTCS_TDSTB (1<<6)
#define SADTCS_TBIU (1<<7)
#define SADRCS_RDEN (1<<0)
#define SADRCS_RDIE (1<<1)
#define SADRCS_RDBDA (1<<3)
#define SADRCS_RDSTA (1<<4)
#define SADRCS_RDBDB (1<<5)
#define SADRCS_RDSTB (1<<6)
#define SADRCS_RBIU (1<<7)
#define SAD_CS_DEN (1<<0)
#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
#define SAD_CS_DSTA (1<<4)
#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
#define SAD_CS_DSTB (1<<6)
#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
#define SAITR_TFS (1<<0)
#define SAITR_RFS (1<<1)
#define SAITR_TUR (1<<2)
#define SAITR_ROR (1<<3)
#define SAITR_CADT (1<<4)
#define SAITR_SADR (1<<5)
#define SAITR_RSTO (1<<6)
#define SAITR_TDBDA (1<<8)
#define SAITR_TDBDB (1<<9)
#define SAITR_RDBDA (1<<10)
#define SAITR_RDBDB (1<<11)
/*
* General-Purpose I/O Interface
*
* Registers
* PA_DDR GPIO Block A Data Direction
* PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
* PA_SDR GPIO Block A Sleep Direction
* PA_SSR GPIO Block A Sleep State
* PB_DDR GPIO Block B Data Direction
* PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
* PB_SDR GPIO Block B Sleep Direction
* PB_SSR GPIO Block B Sleep State
* PC_DDR GPIO Block C Data Direction
* PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
* PC_SDR GPIO Block C Sleep Direction
* PC_SSR GPIO Block C Sleep State
*/
#define PA_DDR SA1111_REG(0x1000)
#define PA_DRR SA1111_REG(0x1004)
#define PA_DWR SA1111_REG(0x1004)
#define PA_SDR SA1111_REG(0x1008)
#define PA_SSR SA1111_REG(0x100c)
#define PB_DDR SA1111_REG(0x1010)
#define PB_DRR SA1111_REG(0x1014)
#define PB_DWR SA1111_REG(0x1014)
#define PB_SDR SA1111_REG(0x1018)
#define PB_SSR SA1111_REG(0x101c)
#define PC_DDR SA1111_REG(0x1020)
#define PC_DRR SA1111_REG(0x1024)
#define PC_DWR SA1111_REG(0x1024)
#define PC_SDR SA1111_REG(0x1028)
#define PC_SSR SA1111_REG(0x102c)
/*
* Interrupt Controller
*
* Registers
* INTTEST0 Test register 0
* INTTEST1 Test register 1
* INTEN0 Interrupt Enable register 0
* INTEN1 Interrupt Enable register 1
* INTPOL0 Interrupt Polarity selection 0
* INTPOL1 Interrupt Polarity selection 1
* INTTSTSEL Interrupt source selection
* INTSTATCLR0 Interrupt Status/Clear 0
* INTSTATCLR1 Interrupt Status/Clear 1
* INTSET0 Interrupt source set 0
* INTSET1 Interrupt source set 1
* WAKE_EN0 Wake-up source enable 0
* WAKE_EN1 Wake-up source enable 1
* WAKE_POL0 Wake-up polarity selection 0
* WAKE_POL1 Wake-up polarity selection 1
*/
#define SA1111_INTTEST0 0x1600
#define SA1111_INTTEST1 0x1604
#define SA1111_INTEN0 0x1608
#define SA1111_INTEN1 0x160c
#define SA1111_INTPOL0 0x1610
#define SA1111_INTPOL1 0x1614
#define SA1111_INTTSTSEL 0x1618
#define SA1111_INTSTATCLR0 0x161c
#define SA1111_INTSTATCLR1 0x1620
#define SA1111_INTSET0 0x1624
#define SA1111_INTSET1 0x1628
#define SA1111_WAKE_EN0 0x162c
#define SA1111_WAKE_EN1 0x1630
#define SA1111_WAKE_POL0 0x1634
#define SA1111_WAKE_POL1 0x1638
#define INTTEST0 SA1111_REG(SA1111_INTTEST0)
#define INTTEST1 SA1111_REG(SA1111_INTTEST1)
#define INTEN0 SA1111_REG(SA1111_INTEN0)
#define INTEN1 SA1111_REG(SA1111_INTEN1)
#define INTPOL0 SA1111_REG(SA1111_INTPOL0)
#define INTPOL1 SA1111_REG(SA1111_INTPOL1)
#define INTTSTSEL SA1111_REG(SA1111_INTTSTSEL)
#define INTSTATCLR0 SA1111_REG(SA1111_INTSTATCLR0)
#define INTSTATCLR1 SA1111_REG(SA1111_INTSTATCLR1)
#define INTSET0 SA1111_REG(SA1111_INTSET0)
#define INTSET1 SA1111_REG(SA1111_INTSET1)
#define WAKE_EN0 SA1111_REG(SA1111_WAKE_EN0)
#define WAKE_EN1 SA1111_REG(SA1111_WAKE_EN1)
#define WAKE_POL0 SA1111_REG(SA1111_WAKE_POL0)
#define WAKE_POL1 SA1111_REG(SA1111_WAKE_POL1)
/*
* PS/2 Trackpad and Mouse Interfaces
*
* Registers (prefix kbd applies to trackpad interface, mse to mouse)
* KBDCR Control Register
* KBDSTAT Status Register
* KBDDATA Transmit/Receive Data register
* KBDCLKDIV Clock Division Register
* KBDPRECNT Clock Precount Register
* KBDTEST1 Test register 1
* KBDTEST2 Test register 2
* KBDTEST3 Test register 3
* KBDTEST4 Test register 4
* MSECR
* MSESTAT
* MSEDATA
* MSECLKDIV
* MSEPRECNT
* MSETEST1
* MSETEST2
* MSETEST3
* MSETEST4
*
*/
#define KBDCR SA1111_REG(0x0a00)
#define KBDSTAT SA1111_REG(0x0a04)
#define KBDDATA SA1111_REG(0x0a08)
#define KBDCLKDIV SA1111_REG(0x0a0c)
#define KBDPRECNT SA1111_REG(0x0a10)
#define MSECR SA1111_REG(0x0c00)
#define MSESTAT SA1111_REG(0x0c04)
#define MSEDATA SA1111_REG(0x0c08)
#define MSECLKDIV SA1111_REG(0x0c0c)
#define MSEPRECNT SA1111_REG(0x0c10)
#define KBDCR_ENA 0x08
#define KBDCR_FKD 0x02
#define KBDCR_FKC 0x01
#define KBDSTAT_TXE 0x80
#define KBDSTAT_TXB 0x40
#define KBDSTAT_RXF 0x20
#define KBDSTAT_RXB 0x10
#define KBDSTAT_ENA 0x08
#define KBDSTAT_RXP 0x04
#define KBDSTAT_KBD 0x02
#define KBDSTAT_KBC 0x01
#define KBDCLKDIV_DivVal Fld(4,0)
#define MSECR_ENA 0x08
#define MSECR_FKD 0x02
#define MSECR_FKC 0x01
#define MSESTAT_TXE 0x80
#define MSESTAT_TXB 0x40
#define MSESTAT_RXF 0x20
#define MSESTAT_RXB 0x10
#define MSESTAT_ENA 0x08
#define MSESTAT_RXP 0x04
#define MSESTAT_MSD 0x02
#define MSESTAT_MSC 0x01
#define MSECLKDIV_DivVal Fld(4,0)
#define KBDTEST1_CD 0x80
#define KBDTEST1_RC1 0x40
#define KBDTEST1_MC 0x20
#define KBDTEST1_C Fld(2,3)
#define KBDTEST1_T2 0x40
#define KBDTEST1_T1 0x20
#define KBDTEST1_T0 0x10
#define KBDTEST2_TICBnRES 0x08
#define KBDTEST2_RKC 0x04
#define KBDTEST2_RKD 0x02
#define KBDTEST2_SEL 0x01
#define KBDTEST3_ms_16 0x80
#define KBDTEST3_us_64 0x40
#define KBDTEST3_us_16 0x20
#define KBDTEST3_DIV8 0x10
#define KBDTEST3_DIn 0x08
#define KBDTEST3_CIn 0x04
#define KBDTEST3_KD 0x02
#define KBDTEST3_KC 0x01
#define KBDTEST4_BC12 0x80
#define KBDTEST4_BC11 0x40
#define KBDTEST4_TRES 0x20
#define KBDTEST4_CLKOE 0x10
#define KBDTEST4_CRES 0x08
#define KBDTEST4_RXB 0x04
#define KBDTEST4_TXB 0x02
#define KBDTEST4_SRX 0x01
#define MSETEST1_CD 0x80
#define MSETEST1_RC1 0x40
#define MSETEST1_MC 0x20
#define MSETEST1_C Fld(2,3)
#define MSETEST1_T2 0x40
#define MSETEST1_T1 0x20
#define MSETEST1_T0 0x10
#define MSETEST2_TICBnRES 0x08
#define MSETEST2_RKC 0x04
#define MSETEST2_RKD 0x02
#define MSETEST2_SEL 0x01
#define MSETEST3_ms_16 0x80
#define MSETEST3_us_64 0x40
#define MSETEST3_us_16 0x20
#define MSETEST3_DIV8 0x10
#define MSETEST3_DIn 0x08
#define MSETEST3_CIn 0x04
#define MSETEST3_KD 0x02
#define MSETEST3_KC 0x01
#define MSETEST4_BC12 0x80
#define MSETEST4_BC11 0x40
#define MSETEST4_TRES 0x20
#define MSETEST4_CLKOE 0x10
#define MSETEST4_CRES 0x08
#define MSETEST4_RXB 0x04
#define MSETEST4_TXB 0x02
#define MSETEST4_SRX 0x01
/*
* PCMCIA Interface
*
* Registers
* PCSR Status Register
* PCCR Control Register
* PCSSR Sleep State Register
*/
#define PCCR SA1111_REG(0x1800)
#define PCSSR SA1111_REG(0x1804)
#define PCSR SA1111_REG(0x1808)
#define PCSR_S0_READY (1<<0)
#define PCSR_S1_READY (1<<1)
#define PCSR_S0_DETECT (1<<2)
#define PCSR_S1_DETECT (1<<3)
#define PCSR_S0_VS1 (1<<4)
#define PCSR_S0_VS2 (1<<5)
#define PCSR_S1_VS1 (1<<6)
#define PCSR_S1_VS2 (1<<7)
#define PCSR_S0_WP (1<<8)
#define PCSR_S1_WP (1<<9)
#define PCSR_S0_BVD1 (1<<10)
#define PCSR_S0_BVD2 (1<<11)
#define PCSR_S1_BVD1 (1<<12)
#define PCSR_S1_BVD2 (1<<13)
#define PCCR_S0_RST (1<<0)
#define PCCR_S1_RST (1<<1)
#define PCCR_S0_FLT (1<<2)
#define PCCR_S1_FLT (1<<3)
#define PCCR_S0_PWAITEN (1<<4)
#define PCCR_S1_PWAITEN (1<<5)
#define PCCR_S0_PSE (1<<6)
#define PCCR_S1_PSE (1<<7)
#define PCSSR_S0_SLEEP (1<<0)
#define PCSSR_S1_SLEEP (1<<1)
#endif
--- sa11x0.h DELETED ---
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 23:00:55
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv9035/src/blob
Added Files:
csir_ims.c gpio-pxa.S
Log Message:
Added new files, removed old stale files
--- NEW FILE: csir_ims.c ---
/*
* -*- eval: c_set_style("linux") -*-
*
* csir_ims.c: CSIR Incident Management System specific stuff
*
* Copyright (C) 2003 Abraham van der Merwe <ab...@4d...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/main.h>
#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/util.h>
#include <blob/reboot.h>
#include <blob/serial.h>
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/command.h>
#include <blob/uucodec.h>
#include <blob/led.h>
#define GPIO25_LED GPIO_bit(25)
static int led_state;
static int led_locked;
static void csir_ims_led_on (void)
{
if (!led_locked) {
GPSR0 = GPIO25_LED;
led_state = 1;
}
}
static void csir_ims_led_off (void)
{
if (!led_locked) {
GPCR0 = GPIO25_LED;
led_state = 0;
}
}
static void csir_ims_led_toggle (void)
{
if (led_state)
csir_ims_led_off ();
else
csir_ims_led_on ();
}
static void csir_ims_led_lock (void)
{
led_locked = 1;
}
static void csir_ims_led_unlock (void)
{
led_locked = 0;
}
static led_driver_t csir_ims_led_driver = {
.led_on = csir_ims_led_on,
.led_off = csir_ims_led_off,
.led_toggle = csir_ims_led_toggle,
.led_lock = csir_ims_led_lock,
.led_unlock = csir_ims_led_unlock
};
static void csir_ims_init_driver (void)
{
static const flash_descriptor_t flash[] = {
{
.size = 128 * 1024,
.num = 64,
.lockable = 1
},
{ /* NULL block */ }
};
GPDR0 |= GPIO25_LED;
flash_descriptors = flash;
reboot_driver = &pxa_reboot_driver;
serial_driver = &pxa_serial_driver;
flash_driver = &intel16_flash_driver;
led_driver = &csir_ims_led_driver;
}
__initlist (csir_ims_init_driver,INIT_LEVEL_DRIVER_SELECTION);
--- NEW FILE: gpio-pxa.S ---
/*
* gpio-pxa.S - Part of the AVO Architecture Boot Loader
*
* Written by Abraham van der Merwe <ab...@bl...>
* Copyright (c) 2002, 2003 Blio Corporation (Pty) Ltd.
* All Rights Reserved.
*/
#ifdef HAVE_CONFIG_H
#include <blob/config.h>
#endif
#include <blob/arch.h>
.text
REG_BASE:
.word GPDR0, GPDR1, GPDR2
.word GPSR0, GPSR1, GPSR2
.word GPCR0, GPCR1, GPCR2
.word GAFR0_L, GAFR1_L, GAFR2_L
.word GAFR0_U, GAFR1_U, GAFR2_U
VALUE_BASE:
.word GPDR0_VALUE, GPDR1_VALUE, GPDR2_VALUE
.word GPSR0_VALUE, GPSR1_VALUE, GPSR2_VALUE
.word GPCR0_VALUE, GPCR1_VALUE, GPCR2_VALUE
.word GAFR0_L_VALUE, GAFR1_L_VALUE, GAFR2_L_VALUE
.word GAFR0_U_VALUE, GAFR1_U_VALUE, GAFR2_U_VALUE
.globl gpiosetup
.type gpiosetup, #function
gpiosetup:
ldr r1, REG_BASE
ldr r0, VALUE_BASE
mov r2, r0
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r1, r2
blo 0b
ldr r1, =PSSR
mov r0, #(PSSR_RDH | PSSR_PH)
str r0, [r1]
mov pc, lr
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 23:00:55
|
Update of /cvsroot/blob/blob/include/blob/arch In directory sc8-pr-cvs1:/tmp/cvs-serv9035/include/blob/arch Added Files: csir_ims.h Log Message: Added new files, removed old stale files --- NEW FILE: csir_ims.h --- /* * csir_ims.h: CSIR Incident Management System * * Copyright (C) 2001 Erik Mouw (J.A...@it...) * Copyright (C) 2002 Holger Schurig <h.s...@mn...> * Copyright (C) 2002 Jeff Sutherland <je...@ac...> * Copyright (C) 2003 Abraham vd Merwe <ab...@4d...> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef BLOB_ARCH_CSIR_IMS_H #define BLOB_ARCH_CSIR_IMS_H #define USE_SERIAL1 #define TERMINAL_SPEED baud_115200 /* the base address were BLOB is loaded by the first stage loader */ #define BLOB_ABS_BASE_ADDR (0xa0200400) /* where do various parts live in RAM */ #define BOOT_PARAMS (0xa0000100) #define BLOB_RAM_BASE (0xa0100000) #define PARAM_RAM_BASE (0xa0200000) #define KERNEL_RAM_BASE (0xa0800000) #define RAMDISK_RAM_BASE (0xa1000000) /* and where do they live in flash */ #define BLOB_FLASH_BASE (0x00000000) #define BLOB_FLASH_LEN (128 * 1024) #define PARAM_FLASH_BASE (BLOB_FLASH_BASE + BLOB_FLASH_LEN) #define PARAM_FLASH_LEN (128 * 1024) #define KERNEL_FLASH_BASE (PARAM_FLASH_BASE + PARAM_FLASH_LEN) #define KERNEL_FLASH_LEN (1024 * 1024) #define RAMDISK_FLASH_BASE (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN) #define RAMDISK_FLASH_LEN (4 * 1024 * 1024) /* load ramdisk into ram */ #define LOAD_RAMDISK 1 /* the size (in kbytes) to which the compressed ramdisk expands */ #define RAMDISK_SIZE (4 * 1024) #if 0 #define MSC0_VALUE 0x #define MSC1_VALUE 0x #define MSC2_VALUE 0x #define MECR_VALUE 0x #define MCMEM0_VALUE 0x #define MCMEM1_VALUE 0x #define MCATT0_VALUE 0x #define MCATT1_VALUE 0x #define MCIO0_VALUE 0x #define MCIO1_VALUE 0x #endif #define MDREFR_VALUE 0x01018013 #define MDCNFG_VALUE 0x000019c9 #define MDMRS_VALUE 0x00020002 #define _U(x) GPIO_INPUT /* GPIO configuration */ #define GPIO0_VALUE _U(GPIO_OUT_LO) #define GPIO1_VALUE _U(GPIO_OUT_LO) #define GPIO2_VALUE _U(GPIO_OUT_LO) #define GPIO3_VALUE GPIO_INPUT /* eth_wakeup */ #define GPIO4_VALUE GPIO_INPUT /* bank_switch_int */ #define GPIO5_VALUE GPIO_INPUT /* eth_link_status */ #define GPIO6_VALUE _U(GPIO_OUT_LO) #define GPIO7_VALUE GPIO_OUT_LO /* cpld_clk */ #define GPIO8_VALUE _U(GPIO_OUT_LO) #define GPIO9_VALUE GPIO_INPUT /* eth_int */ #define GPIO10_VALUE GPIO_OUT_HI /* eth_reset */ #define GPIO11_VALUE _U(GPIO_OUT_LO) #define GPIO12_VALUE GPIO_OUT_LO /* watchdog_strobe */ #define GPIO13_VALUE GPIO_INPUT /* cpld_hw_reset */ #define GPIO14_VALUE GPIO_INPUT /* cpld_?? */ #define GPIO15_VALUE (GPIO_OUT_HI | GPIO_ALT_FN2) /* nCS1 [img_buffer] */ #define GPIO16_VALUE GPIO_OUT_LO #define GPIO17_VALUE GPIO_INPUT /* cpld_?? */ #define GPIO18_VALUE GPIO_INPUT /* vlio_ready_signal */ #define GPIO19_VALUE _U(GPIO_OUT_LO) #define GPIO20_VALUE _U(GPIO_OUT_LO) #define GPIO21_VALUE _U(GPIO_OUT_LO) #define GPIO22_VALUE _U(GPIO_OUT_LO) #define GPIO23_VALUE _U(GPIO_OUT_LO) #define GPIO24_VALUE _U(GPIO_OUT_LO) #define GPIO25_VALUE GPIO_OUT_HI /* LED [debug] */ #define GPIO26_VALUE _U(GPIO_OUT_LO) #define GPIO27_VALUE _U(GPIO_OUT_LO) #define GPIO28_VALUE _U(GPIO_OUT_LO) #define GPIO29_VALUE _U(GPIO_OUT_LO) #define GPIO30_VALUE _U(GPIO_OUT_LO) #define GPIO31_VALUE _U(GPIO_OUT_LO) #define GPIO32_VALUE _U(GPIO_OUT_LO) #define GPIO33_VALUE GPIO_OUT_HI /* nCS5 [unused] */ #define GPIO34_VALUE (GPIO_INPUT | GPIO_ALT_FN1) /* FFRXD */ #define GPIO35_VALUE _U(GPIO_OUT_LO) #define GPIO36_VALUE _U(GPIO_OUT_LO) #define GPIO37_VALUE _U(GPIO_OUT_LO) #define GPIO38_VALUE _U(GPIO_OUT_LO) #define GPIO39_VALUE (GPIO_OUT_LO | GPIO_ALT_FN2) /* FFTXD */ #define GPIO40_VALUE _U(GPIO_OUT_LO) #define GPIO41_VALUE _U(GPIO_OUT_LO) #define GPIO42_VALUE _U(GPIO_OUT_LO) #define GPIO43_VALUE _U(GPIO_OUT_LO) #define GPIO44_VALUE _U(GPIO_OUT_LO) #define GPIO45_VALUE _U(GPIO_OUT_LO) #define GPIO46_VALUE _U(GPIO_OUT_LO) #define GPIO47_VALUE _U(GPIO_OUT_LO) #define GPIO48_VALUE _U(GPIO_OUT_LO) #define GPIO49_VALUE GPIO_OUT_HI /* cpld_pcmcia_pwe */ #define GPIO50_VALUE _U(GPIO_OUT_LO) #define GPIO51_VALUE _U(GPIO_OUT_LO) #define GPIO52_VALUE _U(GPIO_OUT_LO) #define GPIO53_VALUE _U(GPIO_OUT_LO) #define GPIO54_VALUE _U(GPIO_OUT_LO) #define GPIO55_VALUE _U(GPIO_OUT_LO) #define GPIO56_VALUE GPIO_INPUT #define GPIO57_VALUE GPIO_INPUT #define GPIO58_VALUE _U(GPIO_OUT_LO) #define GPIO59_VALUE _U(GPIO_OUT_LO) #define GPIO60_VALUE _U(GPIO_OUT_LO) #define GPIO61_VALUE _U(GPIO_OUT_LO) #define GPIO62_VALUE _U(GPIO_OUT_LO) #define GPIO63_VALUE _U(GPIO_OUT_LO) #define GPIO64_VALUE _U(GPIO_OUT_LO) #define GPIO65_VALUE _U(GPIO_OUT_LO) #define GPIO66_VALUE _U(GPIO_OUT_LO) #define GPIO67_VALUE _U(GPIO_OUT_LO) #define GPIO68_VALUE _U(GPIO_OUT_LO) #define GPIO69_VALUE _U(GPIO_OUT_LO) #define GPIO70_VALUE _U(GPIO_OUT_LO) #define GPIO71_VALUE _U(GPIO_OUT_LO) #define GPIO72_VALUE _U(GPIO_OUT_LO) #define GPIO73_VALUE _U(GPIO_OUT_LO) #define GPIO74_VALUE _U(GPIO_OUT_LO) #define GPIO75_VALUE _U(GPIO_OUT_LO) #define GPIO76_VALUE _U(GPIO_OUT_LO) #define GPIO77_VALUE _U(GPIO_OUT_LO) #define GPIO78_VALUE (GPIO_OUT_HI | GPIO_ALT_FN2) /* nCS2 [img_buffer] */ #define GPIO79_VALUE (GPIO_OUT_HI | GPIO_ALT_FN2) /* nCS3 [eth] */ #define GPIO80_VALUE GPIO_OUT_HI /* nCS4 [unused] */ #define GPIO81_VALUE _U(GPIO_OUT_LO) #define GPIO82_VALUE _U(GPIO_OUT_LO) #define GPIO83_VALUE _U(GPIO_OUT_LO) #define GPIO84_VALUE _U(GPIO_OUT_LO) #endif /* #ifndef BLOB_ARCH_CSIR_IMS_H */ |
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 23:00:54
|
Update of /cvsroot/blob/blob/include/blob In directory sc8-pr-cvs1:/tmp/cvs-serv9035/include/blob Removed Files: sa1100.h sa1111.h Log Message: Added new files, removed old stale files --- sa1100.h DELETED --- --- sa1111.h DELETED --- |
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:58:19
|
Update of /cvsroot/blob/blob/src/diag In directory sc8-pr-cvs1:/tmp/cvs-serv7704/src/diag Modified Files: Makefile.am accelent_sa.c hackkit.c lcd.c regs-sa11x0.c system3.c trizeps.c Log Message: Support for CSIR IMS board and also a working PXA25x port. Still needs some cleaning up and the lubbock and PXA IDP targets are going to be broken by this (not sure if they ever worked and fixing them is trivial). Index: Makefile.am =================================================================== RCS file: /cvsroot/blob/blob/src/diag/Makefile.am,v retrieving revision 1.19 retrieving revision 1.20 diff -u -d -r1.19 -r1.20 --- Makefile.am 26 Nov 2002 18:52:53 -0000 1.19 +++ Makefile.am 6 Aug 2003 22:55:41 -0000 1.20 @@ -75,7 +75,8 @@ shannon.c \ system3.c \ trizeps.c \ - pxa_idp.c + pxa_idp.c \ + csir_ims.c diag_elf32_DEPENDENCIES = \ @DIAG_LCD_OBJS@ \ Index: accelent_sa.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/accelent_sa.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- accelent_sa.c 11 Feb 2002 16:53:16 -0000 1.2 +++ accelent_sa.c 6 Aug 2003 22:55:41 -0000 1.3 @@ -37,7 +37,7 @@ #include <blob/init.h> #include <blob/serial.h> #include <blob/time.h> -#include <blob/sa1100.h> +#include <blob/arch.h> Index: hackkit.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/hackkit.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- hackkit.c 26 Nov 2002 18:18:23 -0000 1.1 +++ hackkit.c 6 Aug 2003 22:55:41 -0000 1.2 @@ -35,7 +35,7 @@ #include <blob/arch.h> #include <blob/serial.h> #include <blob/init.h> -#include <blob/sa1100.h> +#include <blob/arch.h> /********************************************************************** * defines Index: lcd.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/lcd.c,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- lcd.c 27 May 2002 09:59:33 -0000 1.7 +++ lcd.c 6 Aug 2003 22:55:41 -0000 1.8 @@ -34,7 +34,7 @@ #include <blob/util.h> #include <blob/command.h> #include <blob/serial.h> -#include <blob/sa1100.h> +#include <blob/arch.h> #include <blob/lcd.h> Index: regs-sa11x0.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/regs-sa11x0.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- regs-sa11x0.c 17 Feb 2002 20:03:41 -0000 1.5 +++ regs-sa11x0.c 6 Aug 2003 22:55:41 -0000 1.6 @@ -37,7 +37,7 @@ #include <blob/init.h> #include <blob/serial.h> #include <blob/time.h> -#include <blob/sa1100.h> +#include <blob/arch.h> /********************************************************************** * defines Index: system3.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/system3.c,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- system3.c 11 Feb 2002 16:53:16 -0000 1.10 +++ system3.c 6 Aug 2003 22:55:41 -0000 1.11 @@ -38,7 +38,7 @@ #include <blob/init.h> #include <blob/serial.h> #include <blob/time.h> -#include <blob/sa1100.h> +#include <blob/arch.h> #include <blob/sa1111.h> #include <blob/lcd.h> Index: trizeps.c =================================================================== RCS file: /cvsroot/blob/blob/src/diag/trizeps.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- trizeps.c 23 Apr 2002 13:29:57 -0000 1.1 +++ trizeps.c 6 Aug 2003 22:55:41 -0000 1.2 @@ -36,7 +36,7 @@ #include <blob/serial.h> #include <blob/time.h> -// #include <blob/sa1100.h> +// #include <blob/arch.h> // #include <blob/sa1111.h> // #include <blob/lcd.h> |
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:58:19
|
Update of /cvsroot/blob/blob/utils/build In directory sc8-pr-cvs1:/tmp/cvs-serv7704/utils/build Modified Files: build_Makefile build_all Log Message: Support for CSIR IMS board and also a working PXA25x port. Still needs some cleaning up and the lubbock and PXA IDP targets are going to be broken by this (not sure if they ever worked and fixing them is trivial). Index: build_Makefile =================================================================== RCS file: /cvsroot/blob/blob/utils/build/build_Makefile,v retrieving revision 1.15 retrieving revision 1.16 diff -u -d -r1.15 -r1.16 --- build_Makefile 4 Jan 2003 00:28:46 -0000 1.15 +++ build_Makefile 6 Aug 2003 22:55:41 -0000 1.16 @@ -15,7 +15,7 @@ archs = \ accelent_sa assabet neponset badge4 brutus cep creditlart frodo \ hackkit h3600 idr jornada720 lart lubbock miniprint nesa pleb \ - pxa_idp shannon system3 trizeps + pxa_idp csir_ims shannon system3 trizeps debug-archs = $(foreach a, $(archs), $(a)-debug) all-archs = $(archs) $(debug-archs) Index: build_all =================================================================== RCS file: /cvsroot/blob/blob/utils/build/build_all,v retrieving revision 1.15 retrieving revision 1.16 diff -u -d -r1.15 -r1.16 --- build_all 4 Jan 2003 00:28:46 -0000 1.15 +++ build_all 6 Aug 2003 22:55:41 -0000 1.16 @@ -12,7 +12,7 @@ # published by the Free Software Foundation. # -archs="accelent_sa assabet neponset badge4 brutus cep creditlart frodo hackkit h3600 idr jornada720 lart lubbock miniprint nesa pleb pxa_idp shannon system3 trizeps" +archs="accelent_sa assabet neponset badge4 brutus cep creditlart frodo hackkit h3600 idr jornada720 lart lubbock miniprint nesa pleb pxa_idp csir_ims shannon system3 trizeps" linux_prefix=~/LART/build/linux/elinux blob_src=~/src/sourceforge/blob extra_flags="--enable-all-features --with-commands=all" |
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:58:19
|
Update of /cvsroot/blob/blob/src/lib
In directory sc8-pr-cvs1:/tmp/cvs-serv7704/src/lib
Modified Files:
Makefile.am i2c-gpio.c i2c.c icache.c led-sa11x0.c led.c
reboot-sa11x0.c serial-pxa.c serial-sa11x0.c time.c
Log Message:
Support for CSIR IMS board and also a working PXA25x port. Still needs some
cleaning up and the lubbock and PXA IDP targets are going to be broken by
this (not sure if they ever worked and fixing them is trivial).
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/Makefile.am,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -d -r1.27 -r1.28
--- Makefile.am 3 Apr 2003 14:58:17 -0000 1.27
+++ Makefile.am 6 Aug 2003 22:55:41 -0000 1.28
@@ -30,8 +30,6 @@
crc32.c \
error.c \
ext2fs.c \
- i2c-gpio.c \
- i2c.c \
icache.c \
init.c \
led.c \
@@ -69,6 +67,8 @@
gio_part_blob.c \
gio_ram.c \
gio_flash.c \
+ i2c-gpio.c \
+ i2c.c \
tar.c
Index: i2c-gpio.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/i2c-gpio.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- i2c-gpio.c 24 Jan 2003 10:03:29 -0000 1.3
+++ i2c-gpio.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -28,7 +28,7 @@
#include <blob/i2c.h>
#include <blob/i2c-gpio.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/util.h>
Index: i2c.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/i2c.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- i2c.c 2 May 2002 01:45:39 -0000 1.4
+++ i2c.c 6 Aug 2003 22:55:41 -0000 1.5
@@ -169,7 +169,7 @@
bit = get_sda(bus);
if (bit)
- printf(__FUNCTION__ ": did not get ack\n");
+ printf("%s: did not get ack\n",__FUNCTION__);
set_scl(bus, 0);
Index: icache.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/icache.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- icache.c 7 Oct 2001 20:16:57 -0000 1.3
+++ icache.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -30,7 +30,7 @@
#include <blob/icache.h>
#include <blob/types.h>
-
+#include<blob/util.h>
void enable_icache(void)
{
Index: led-sa11x0.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/led-sa11x0.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- led-sa11x0.c 13 Feb 2003 01:10:53 -0000 1.1
+++ led-sa11x0.c 6 Aug 2003 22:55:41 -0000 1.2
@@ -33,7 +33,6 @@
#endif
#include <blob/arch.h>
-#include <blob/sa1100.h>
#include <blob/led.h>
#include <blob/init.h>
Index: led.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/led.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- led.c 13 Feb 2003 01:10:53 -0000 1.8
+++ led.c 6 Aug 2003 22:55:41 -0000 1.9
@@ -33,17 +33,15 @@
led_driver_t *led_driver;
-int led_init(void)
+void led_init(void)
{
if (led_driver == NULL){
deprintf("No LED driver defined in arch specific file\n");
- return -1;
+ return;
}
led_driver->led_unlock();
led_driver->led_on();
-
- return 0;
}
int led_on(void)
Index: reboot-sa11x0.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/reboot-sa11x0.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- reboot-sa11x0.c 4 Jan 2003 02:11:43 -0000 1.1
+++ reboot-sa11x0.c 6 Aug 2003 22:55:41 -0000 1.2
@@ -27,7 +27,7 @@
# include <blob/config.h>
#endif
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/reboot.h>
Index: serial-pxa.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/serial-pxa.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- serial-pxa.c 14 Aug 2002 21:13:45 -0000 1.3
+++ serial-pxa.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -101,8 +101,7 @@
static int pxa_serial_flush_output(void)
{
/* wait until the transmitter is no longer busy */
- while(SerialLSR & ~LSR_TDRQ) {
- }
+ while(SerialLSR & ~LSR_TDRQ) ;
return 0;
}
@@ -115,6 +114,11 @@
{
u32 divisor;
+#ifdef USE_SERIAL1
+ /* enable clock */
+ CKEN |= CKEN6_FFUART;
+#endif
+
/* get correct divisor */
switch(baud) {
case baud_1200:
@@ -149,29 +153,26 @@
return -ERANGE;
}
- pxa_serial_flush_output();
-
/* switch receiver and transmitter off */
- SerialIER = 0x00;
+ SerialLCR = 0;
+ SerialIER = 0;
+ SerialFIFO = 0;
/* Gain access to divisor latch */
- SerialLCR = LCR_DLAB;
+ SerialLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
/* Load baud rate divisor in two steps, lsb, then msb of value */
SerialDATA = divisor & 0xff;
- SerialIER = (divisor & 0xff00) >> 8;
+ SerialIER = (divisor >> 8) & 0xff;
/* set the port to sensible defaults (no break, no interrupts,
* no parity, 8 databits, 1 stopbit, transmitter and receiver
* enabled), reset dlab bit:
*/
- SerialLCR = ( LCR_WLS1 | LCR_WLS0 );
+ SerialLCR = LCR_WLS1 | LCR_WLS0;
- /* turn on tx/rx fifo's */
- SerialFIFO = FCR_TRFIFOE;
-
/* turn the receiver and transmitter back on */
SerialIER = IER_UUE;
Index: serial-sa11x0.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/serial-sa11x0.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- serial-sa11x0.c 1 Feb 2002 14:38:55 -0000 1.3
+++ serial-sa11x0.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -29,7 +29,7 @@
#include <blob/arch.h>
#include <blob/errno.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/serial.h>
#include <blob/types.h>
Index: time.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c 7 Oct 2001 20:16:57 -0000 1.3
+++ time.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -37,17 +37,11 @@
#include <blob/init.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/time.h>
-
-
-
static int numOverflows;
-
-
-
void TimerInit(void)
{
/* clear counter */
@@ -57,8 +51,7 @@
OIER = 0;
/* wait until OSCR > 0 */
- while(OSCR == 0)
- ;
+ while(OSCR == 0) ;
/* clear match register 0 */
OSMR0 = 0;
@@ -69,9 +62,6 @@
numOverflows = 0;
}
-
-
-
/* returns the time in 1/TICKS_PER_SECOND seconds */
u32 TimerGetTime(void)
{
@@ -84,16 +74,11 @@
return((u32) OSCR);
}
-
-
-
int TimerDetectOverflow(void)
{
return(OSSR & OSSR_M0);
}
-
-
void TimerClearOverflow(void)
{
if(TimerDetectOverflow())
@@ -102,8 +87,6 @@
OSSR = OSSR_M0;
}
-
-
void msleep(unsigned int msec)
{
u32 ticks, start, end;
@@ -141,3 +124,4 @@
reached = 1;
} while(!reached);
}
+
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:55:44
|
Update of /cvsroot/blob/blob/src/blob
In directory sc8-pr-cvs1:/tmp/cvs-serv7704/src/blob
Modified Files:
Makefile.am badge4.c chain.S clock.c dafit.c hackkit.c idr.c
initcalls.c jornada720.c load_kernel.c memsetup-pxa250.S
pxa_idp.c start-pxa.S start-sa11x0.S start.S system3.c
Log Message:
Support for CSIR IMS board and also a working PXA25x port. Still needs some
cleaning up and the lubbock and PXA IDP targets are going to be broken by
this (not sure if they ever worked and fixing them is trivial).
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.39
retrieving revision 1.40
diff -u -d -r1.39 -r1.40
--- Makefile.am 3 Apr 2003 15:02:57 -0000 1.39
+++ Makefile.am 6 Aug 2003 22:55:41 -0000 1.40
@@ -25,14 +25,13 @@
blob-rest-elf32 \
blob-rest \
blob-elf32 \
- blob \
- blob-chain-elf32 \
- blob-chain
+ blob
INCLUDES += \
-I${top_builddir}/include \
- -I${top_srcdir}/include
+ -I${top_srcdir}/include \
+ -I${LINUX_INCLUDE}
# ---- Built sources -------------------------------------------------
@@ -43,7 +42,7 @@
rest-ld-script: rest-ld-script.in
- $(CC) -x c-header -undef -nostdinc ${INCLUDES} -E $< | sed 's/^#.*//' > $@
+ $(CC) -x c-header -undef -nostdinc ${INCLUDES} -D__ASSEMBLY__ -E $< | sed 's/^#.*//' > $@
commands.c:
${top_srcdir}/src/commands/make_commands.sh @BLOB_COMMANDS@ > $@
@@ -88,7 +87,7 @@
smc9196.c \
accelent_sa.c assabet.c brutus.c badge4.c cep.c clart.c dafit.c frodo.c \
hackkit.c h3600.c idr.c jornada720.c lart.c miniprint.c nesa.c pleb.c \
- shannon.c system3.c trizeps.c pxa_idp.c
+ shannon.c system3.c trizeps.c pxa_idp.c csir_ims.c
blob_rest_elf32_DEPENDENCIES = \
@@ -154,6 +153,7 @@
memsetup-sa1100.S \
memsetup-sa1110.S \
start-pxa.S \
+ gpio-pxa.S \
start-sa11x0.S
blob_elf32_DEPENDENCIES = \
@@ -178,38 +178,6 @@
blob: blob-elf32
- $(OBJCOPY) $(OCFLAGS) $< $@
-
-
-# ---- Blob first stage chain loader --------------------------------
-
-# WARNING: chain.S *must* be the first file, otherwise the target will
-# be linked in the wrong order!
-blob_chain_elf32_SOURCES = \
- chain.S
-
-EXTRA_blob_chain_elf32_SOURCES= \
- ledasm-mmap.S \
- ledasm-sa11x0.S
-
-blob_chain_elf32_DEPENDENCIES =\
- start-ld-script \
- @BLOB_LED_STARTCODE@ \
- blob-rest-piggy.o
-
-blob_chain_elf32_LDFLAGS += \
- -Wl,-T,${srcdir}/start-ld-script \
- -Wl,-Map,blob-start-chain-elf32.map
-
-blob_chain_elf32_LDADD += \
- @BLOB_LED_STARTCODE@ \
- -lgcc
-
-
-blob_chain_SOURCES =
-
-
-blob-chain: blob-chain-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
Index: badge4.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/badge4.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- badge4.c 13 Feb 2003 01:10:53 -0000 1.16
+++ badge4.c 6 Aug 2003 22:55:41 -0000 1.17
@@ -29,7 +29,7 @@
#include <blob/arch/badge4.h>
#include <blob/flash.h>
#include <blob/init.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/reboot.h>
#include <blob/serial.h>
#include <blob/util.h>
Index: chain.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/chain.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- chain.S 10 Feb 2003 23:07:05 -0000 1.3
+++ chain.S 6 Aug 2003 22:55:41 -0000 1.4
@@ -58,7 +58,7 @@
#endif
/* init LED */
- bl ledinit
+ //bl ledinit
/* assume that the CPU and the memory are already set up at
* this point. also assume that interrupts are disabled, and if
@@ -95,7 +95,7 @@
/* turn off the LED. if it stays off it is an indication that
* we didn't make it into the C code
*/
- bl led_off
+ //bl led_off
/* blob is copied to ram, so jump to it */
Index: clock.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/clock.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- clock.c 7 Oct 2001 23:01:08 -0000 1.3
+++ clock.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -39,7 +39,7 @@
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/types.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/util.h>
Index: dafit.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/dafit.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- dafit.c 11 Apr 2003 21:24:12 -0000 1.2
+++ dafit.c 6 Aug 2003 22:55:41 -0000 1.3
@@ -46,8 +46,8 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
-#include <blob/sa1111.h>
+#include <blob/arch.h>
+#include <blob/proc/sa1111.h>
#include <blob/generic_io.h>
Index: hackkit.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/hackkit.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- hackkit.c 13 Feb 2003 01:10:53 -0000 1.4
+++ hackkit.c 6 Aug 2003 22:55:41 -0000 1.5
@@ -46,7 +46,7 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
/**********************************************************************
* defines
Index: idr.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/idr.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- idr.c 13 Feb 2003 01:10:53 -0000 1.12
+++ idr.c 6 Aug 2003 22:55:41 -0000 1.13
@@ -30,7 +30,7 @@
#include <blob/init.h>
#include <blob/reboot.h>
#include <blob/serial.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/sa1111.h>
#include <blob/led.h>
Index: initcalls.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/initcalls.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- initcalls.c 3 Apr 2003 14:58:16 -0000 1.5
+++ initcalls.c 6 Aug 2003 22:55:41 -0000 1.6
@@ -35,17 +35,11 @@
#include <blob/time.h>
#include <blob/gio_drivers.h>
-
-
-
/* default serial initialisation */
static void serial_default_init(void)
{
serial_init(TERMINAL_SPEED);
}
-
-
-
/* init calls */
__initlist(serial_default_init, INIT_LEVEL_INITIAL_HARDWARE);
Index: jornada720.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/jornada720.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- jornada720.c 13 Feb 2003 01:10:53 -0000 1.7
+++ jornada720.c 6 Aug 2003 22:55:41 -0000 1.8
@@ -28,7 +28,7 @@
#include <blob/flash.h>
#include <blob/init.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/reboot.h>
#include <blob/serial.h>
#include <blob/time.h>
Index: load_kernel.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/load_kernel.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- load_kernel.c 28 Jan 2003 04:58:26 -0000 1.15
+++ load_kernel.c 6 Aug 2003 22:55:41 -0000 1.16
@@ -110,7 +110,7 @@
}
if (!p) {
- eprintf("Unable to find kernel");
+ eprintf("Unable to find kernel\n");
return EINVAL;
}
Index: memsetup-pxa250.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-pxa250.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- memsetup-pxa250.S 14 Aug 2002 21:04:23 -0000 1.1
+++ memsetup-pxa250.S 6 Aug 2003 22:55:41 -0000 1.2
@@ -1,262 +1,225 @@
+
/*
- * Ripped from RedBoot, will add disclaimer later
+ * memory-pxa.S - Part of the AVO Architecture Boot Loader
+ *
+ * Written by Abraham van der Merwe <ab...@bl...>
+ * Copyright (c) 2002, 2003 Blio Corporation (Pty) Ltd.
+ * All Rights Reserved.
*/
#ifdef HAVE_CONFIG_H
-# include <blob/config.h>
+#include <blob/config.h>
#endif
#include <blob/arch.h>
.text
-.globl memsetup
-
-@****************************************************************************
-@ Initlialize Memory Controller
-@ The sequence below is based on the recommended init steps detailed in the
-@ PXA Processor Developers Manual section 6.12
-@
-
-memsetup:
-
- @ pause for 200 uSecs to allow internal clocks to settle
-
- ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec,
- @ so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- @ get memory controller base address
- ldr r1, =MEMC_BASE_PHYSICAL
-
-@*****************************************************************************
-@ Step 1
-@
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
+#define MDCNFG_OFFSET 0x00
+#define MDREFR_OFFSET 0x04
+#define MSC0_OFFSET 0x08
+#define MSC1_OFFSET 0x0c
+#define MSC2_OFFSET 0x10
+#define MECR_OFFSET 0x14
+#define SXLCR_OFFSET 0x18
+#define SXCNFG_OFFSET 0x1c
+#define SXMRS_OFFSET 0x24
+#define MCMEM0_OFFSET 0x28
+#define MCMEM1_OFFSET 0x2c
+#define MCATT0_OFFSET 0x30
+#define MCATT1_OFFSET 0x34
+#define MCIO0_OFFSET 0x38
+#define MCIO1_OFFSET 0x3c
+#define MDMRS_OFFSET 0x40
- @ write msc1
- ldr r2, =MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
+/*
+ * The sequence below is based on the recommended init steps detailed
+ * in the Intel PXA255 Processor Developer's Manual Section 6.11
+ */
- @ write msc2
- ldr r2, =MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
+.macro wait
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, #768
+ bls 0b
+.endm
- @ write mecr
- ldr r2, =MECR_VAL
- str r2, [r1, #MECR_OFFSET]
+/*
+ * memory_setup - Initialize Memory (SDRAM, static memory, flash, etc)
+ *
+ * INPUT: none
+ * OUTPUT: none
+ * TRASHED: r0 - r4
+ */
+.globl memsetup
+.type memsetup, #function
+memsetup:
+ /* wait for internal clocks to stabilize */
+ wait
- @ write mcmem0
- ldr r2, =MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
+ ldr r1, =0x48000000
- @ write mcmem1
- ldr r2, =MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
+ /* write MSC0, read back to ensure data latches */
+#ifdef MSC0_VALUE
+ ldr r0, =MSC0_VALUE
+ str r0, [r1, #MSC0_OFFSET]
+ ldr r0, [r1, #MSC0_OFFSET]
+#endif /* #ifdef MSC0_VALUE */
- @ write mcatt0
- ldr r2, =MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
+ /* write MSC1, read back to ensure data latches */
+#ifdef MSC1_VALUE
+ ldr r0, =MSC1_VALUE
+ str r0, [r1, #MSC1_OFFSET]
+ ldr r0, [r1, #MSC1_OFFSET]
+#endif /* #ifdef MSC1_VALUE */
- @ write mcatt1
- ldr r2, =MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
+ /* write MSC2, read back to ensure data latches */
+#ifdef MSC2_VALUE
+ ldr r0, =MSC2_VALUE
+ str r0, [r1, #MSC2_OFFSET]
+ ldr r0, [r1, #MSC2_OFFSET]
+#endif /* #ifdef MSC2_VALUE */
- @ write mcio0
- ldr r2, =MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
+ /* write MECR */
+#ifdef MECR_VALUE
+ ldr r0, =MECR_VALUE
+ str r0, [r1, #MECR_OFFSET]
+#endif /* #ifdef MECR_VALUE */
- @ write mcio1
- ldr r2, =MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
+ /* write MCMEM0 */
+#ifdef MCMEM0_VALUE
+ ldr r0, =MCMEM0_VALUE
+ str r0, [r1, #MCMEM0_OFFSET]
+#endif /* #ifdef MCMEM0_VALUE */
- @*********************************************************************
- @ Step 1, 3rd bullet
- @
+ /* write MCMEM1 */
+#ifdef MCMEM1_VALUE
+ ldr r0, =MCMEM1_VALUE
+ str r0, [r1, #MCMEM1_OFFSET]
+#endif /* #ifdef MCMEM1_VALUE */
- @ get the mdrefr settings (k0run, e0pin, etc.)
- ldr r3, =MDREFR_VAL
+ /* write MCATT0 */
+#ifdef MCATT0_VALUE
+ ldr r0, =MCATT0_VALUE
+ str r0, [r1, #MCATT0_OFFSET]
+#endif /* #ifdef MCATT0_VALUE */
- @ extract DRI field (we need a valid DRI field)
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- orr r4, r4, r3
-
- @ write back mdrefr
- str r4, [r1, #MDREFR_OFFSET]
+ /* write MCATT1 */
+#ifdef MCATT1_VALUE
+ ldr r0, =MCATT1_VALUE
+ str r0, [r1, #MCATT1_OFFSET]
+#endif /* #ifdef MCATT1_VALUE */
- @ *Note: preserve the mdrefr value in r4 *
+ /* write MCIO0 */
+#ifdef MCIO0_VALUE
+ ldr r0, =MCIO0_VALUE
+ str r0, [r1, #MCIO0_OFFSET]
+#endif /* #ifdef MCIO0_VALUE */
-@*****************************************************************************
-@ Step 2
-@ I dont know why, but this was commented out in RedBoot
-@
- @ fetch sxcnfg value
- @
- @ldr r2, =0
- @ write back sxcnfg
- @str r2, [r1, #SXCNFG_OFFSET]
+ /* write MCIO1 */
+#ifdef MCIO1_VALUE
+ ldr r0, =MCIO1_VALUE
+ str r0, [r1, #MCIO1_OFFSET]
+#endif /* #ifdef MCIO1_VALUE */
- @ if sxcnfg=0, do not program for synch-static memory
- @cmp r2, #0
- @beq 1f
+ /* get the mdrefr settings (k0run, e0pin, etc.) */
+ ldr r3, =MDREFR_VALUE
- @program sxmrs
- @ldr r2, =SXMRS_SETTINGS
- @str r2, [r1, #SXMRS_OFFSET]
+ /* extract DRI field (we need a valid DRI field) */
+ ldr r2, =0xfff
+ and r3, r3, r2
+ /* get the reset state of MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
-@*****************************************************************************
-@ Step 3
-@ I am hard-coding in 50/100/300 clock speeds for now.
-@ This needs testing since I hacked up a large, ugly version of this that was
-@ Lubbock-specific. -Rusty
-@
+ /* clear the DRI field */
+ bic r4, r4, r2
- @ Assumes previous MDREFR value in r4, if not then read current MDREFR
+ /* insert the valid DRI field loaded above */
+ orr r4, r4, r3
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free)
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K1RUN if bank 0 installed
- orr r4, r4, #0x00010000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
- @ set K1DB2 (SDClk[1] = MemClk/2)
- orreq r4, r4, #0x00020000
+ /*
+ * I am hard-coding in 50/100/300 clock speeds for now.
+ * This needs testing since I hacked up a large, ugly version
+ * of this that was Lubbock-specific. -Rusty
+ */
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
+ /* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
- @ deassert SLFRSH
- bic r4, r4, #0x00400000
-
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
+ /* set K1RUN if bank 0 installed */
+ orr r4, r4, #0x00010000
- @ assert E1PIN
- orr r4, r4, #0x00008000
-
- @ write back MDREFR
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
+ /* set K1DB2 (SDClk[1] = MemClk/2) */
+ orreq r4, r4, #0x00020000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
-@*****************************************************************************
-@ Step 4
-@
- @ fetch platform value of MDCNFG
- ldr r2, =MDCNFG_VAL
+ /* deassert SLFRSH */
+ bic r4, r4, #0x00400000
- @ disable all sdram banks
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
- @ program banks 0/1 for bus width
- bic r2, r2, #MDCNFG_DWID0_32B @ 0=32-bit
+ /* assert E1PIN */
+ orr r4, r4, #0x00008000
+ /* write back MDREFR */
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
- @ write initial value of MDCNFG, w/o enabling sdram banks
- str r2, [r1, #MDCNFG_OFFSET]
+.rept 3
+ nop
+.endr
+ /* fetch platform value of MDCNFG */
+ ldr r2, =MDCNFG_VALUE
-@*****************************************************************************
-@ Step 5
-@
- @ pause for 200 uSecs
- ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec,
- @ so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
+ /* disable all sdram banks */
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-@*****************************************************************************
-@ Step 6
-@
- @ turn everything off (caches off, MMU off, etc.)
- mov r0, #0x78
- mcr p15, 0, r0, c1, c0, 0
+ /* write initial value of MDCNFG, w/o enabling sdram banks */
+ str r2, [r1, #MDCNFG_OFFSET]
+ /* wait for internal clocks to stabilize */
+ wait
-@*****************************************************************************
-@ Step 7
-@
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ CBR is generated for all banks
-
- ldr r2, =SDRAM_BASE_PHYSICAL
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
+ /* turn everything off (caches off, MMU off, etc.) */
+ mov r0, #0x78
+ mcr p15, 0, r0, c1, c0, 0
+ /*
+ * Access memory *not yet enabled* for CBR refresh cycles (8)
+ * CBR is generated for all banks
+ */
-@*****************************************************************************
-@ Step 8: NOP (enable dcache if you wanna... we dont)
-@
+ ldr r2, =PXA_SDRAM_BANK0
+.rept 8
+ str r2, [r2]
+.endr
-@*****************************************************************************
-@ Step 9
-@
- @ get memory controller base address
- ldr r1, =MEMC_BASE_PHYSICAL
+ /* fetch current MDCNFG value */
+ ldr r3, [r1, #MDCNFG_OFFSET]
- @ fetch current mdcnfg value
- ldr r3, [r1, #MDCNFG_OFFSET]
+ /* enable sdram bank 0 if installed (must do for any populated bank) */
+ orr r3, r3, #MDCNFG_DE0
- @ enable sdram bank 0 if installed (must do for any populated bank)
- orr r3, r3, #MDCNFG_DE0
+ /* write back mdcnfg, enabling the sdram bank(s) */
+ str r3, [r1, #MDCNFG_OFFSET]
- @ write back mdcnfg, enabling the sdram bank(s)
- str r3, [r1, #MDCNFG_OFFSET]
+ /* write MDMRS */
+ ldr r2, =MDMRS_VALUE
+ str r2, [r1, #MDMRS_OFFSET]
+ mov pc, lr
-@*****************************************************************************
-@ Step 10
-@
- @ write MDMRS
- ldr r2, =MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
-@*****************************************************************************
-@ Step 11: Final Step
-@ Omitted, used to contain work around for old A0 PXA250 stepping
-@
- @ return
- mov pc, lr
Index: pxa_idp.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/pxa_idp.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pxa_idp.c 13 Feb 2003 01:10:53 -0000 1.3
+++ pxa_idp.c 6 Aug 2003 22:55:41 -0000 1.4
@@ -100,14 +100,14 @@
/* select drivers */
reboot_driver = &pxa_reboot_driver;
serial_driver = &pxa_serial_driver;
- led_driver = &sa11x0_gpio_led_driver;
+ led_driver = /*&sa11x0_gpio_led_driver*/NULL;
}
__initlist(accelent_sa_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
-
+#if 0
/*********************************************************************
* cmd_download_file
*
@@ -243,3 +243,4 @@
static char flasherasehelp[] = "ferase adr size(bytes)\n"
"erase a flash region\n";
__commandlist( cmd_flash_erase, "ferase", flasherasehelp );
+#endif
Index: start-pxa.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-pxa.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- start-pxa.S 14 Aug 2002 21:04:25 -0000 1.1
+++ start-pxa.S 6 Aug 2003 22:55:41 -0000 1.2
@@ -28,214 +28,111 @@
.text
- @ We start by implementing *all* exception vectors
+/*
+ * We start by implementing *all* exception vectors
+ *
+ * Reset vector: this initialises the machine
+ * note here that this not yet taken sleep wakeup into account -- lets just
+ * get something to work first.
+ */
- @ Reset vector: this initialises the machine
- @ note here that this not yet taken sleep wakeup into account -- lets just
- @ get something to work first.
+.macro blink, count
+ mov r3, \count
+ b endless_blink
+.endm
.globl reset
reset:
- @ First, mask **ALL** interrupts
- ldr r0, =ICMR
- mov r1, #0x00
- str r1, [r0]
+ /* First, mask **ALL** interrupts */
+ ldr r0, =ICMR
+ mov r1, #0x00
+ str r1, [r0]
real_reset:
+ bl ledsetup
+ bl memsetup
+ bl normal_boot
-#ifdef LUBBOCK
- @ Lubbock must initialize GPIO before any chip selects will work.
- bl gpio_init
-
- @ now that chip selects will work, turn on lubbock HW registers, SRAM
- @ and ethernet contoller chip selects
- ldr r3, =MSC1
- ldr r2, =MSC1_VAL
- str r2, [r3]
- ldr r2, [r3] @ need to read it back to latch it
-#endif
-
- bl ledinit
-
- @ setup memory
- bl memsetup
-
- @ loop here infinitely until I can get this to compile and boot
- @ TODO: get this to compile and boot.
-crap:
- b crap
-
- @ turn off the LED. if it stays off it is an indication that
- @ we didnt make it into the C code
- bl led_off
-
- @ everything is said and done over here, call normal_boot in
- @ the generic startup code to continue the boot procedure
- bl normal_boot
-
- @ oops, normal_boot returns, something went wrong. signal an
- @ error to the user
- mov r6, #2
- b endless_blink
-
-
-
-
-/* we could choose to handle all exceptions in a nice way, but the
- * best is to treat them as errors because blob should not contain
- * errors
- */
+ blink #1
-/* Undefined instruction exception */
.globl undefined_instruction
undefined_instruction:
- mov r6, #3
- b endless_blink
-
-
-
+ blink #2
-/* SWI */
.globl software_interrupt
software_interrupt:
- /* NOTE: This is NOT an error! If you think that blob should return
- * from software interrupts, you're plain WRONG. The source of the
- * problem is in the kernel: you should *disable* CONFIG_ANGELBOOT
- * simply because blob is not angel. -- Erik
- */
- mov r6, #4
- b endless_blink
-
-
-
+ blink #3
-/* prefetch exception. shouldn't happen though we usually run with
- * i-cache enabled */
.globl prefetch_abort
prefetch_abort:
- mov r6, #5
- b endless_blink
-
-
-
+ blink #4
-/* data abort */
.globl data_abort
data_abort:
- mov r6, #6
- b endless_blink
-
-
-
+ blink #5
-/* we *should* never reach this */
.globl not_used
not_used:
- mov r6, #7
- b endless_blink
-
-
-
+ blink #6
-/* interrupt. we could handle this differently later if some kind of
- * driver in blob wants to be interrupt driven. for the time being we
- * treat it as an error.
- */
.globl irq
irq:
- mov r6, #8
- b endless_blink
-
-
-
+ blink #7
-/* FIQ. same as IRQ */
.globl fiq
fiq:
- mov r6, #9
- b endless_blink
-
-
-
-
-/* endless loop that blinks the LED. r6 contains the number of blinks */
-endless_blink:
- bl wait
- mov r0, r6
- bl led_blink
- b endless_blink
-
-wait:
- /* busy wait loop*/
- mov r5, #0x1000000
-wait0:
- subs r5, r5, #1
- bne wait0
- mov pc, lr
-
-#ifdef LUBBOCK
-@ initialize GPIO. This should be moved to its own file eventually...
-
-init_gpio:
- ldr r0, =GPSR0
- ldr r1, =0x00008000
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =0x00FC0382
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =0x0001FFFF //0x0001C000
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =0x00000000
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =0x0060A800
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =0x00FF0382
- str r1, [r0]
+ blink #8
- ldr r0, =GPDR2
- ldr r1, =0x0001C000
- str r1, [r0]
+#define GPIO25_LED GPIO_bit(25)
- ldr r0, =GAFR0_L
- ldr r1, =0x98400000
- str r1, [r0]
+ledset:
+#ifdef CSIR_IMS
+ ldr r1, =GPSR0
+ mov r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ mov pc, lr
- ldr r0, =GAFR0_U
- ldr r1, =0x00002950
- str r1, [r0]
+ledclear:
+#ifdef CSIR_IMS
+ ldr r1, =GPCR0
+ mov r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ mov pc, lr
- ldr r0, =GAFR1_L
- ldr r1, =0x000A9558
- str r1, [r0]
+ledsetup:
+ mov r2, lr
+#ifdef CSIR_IMS
+ ldr r1, =GPDR0
+ ldr r0, [r1]
+ orr r0, r0, #GPIO25_LED
+ str r0, [r1]
+#endif
+ bl ledclear
+ mov pc, r2
- ldr r0, =GAFR1_U
- ldr r1, =0x0005AAAA
- str r1, [r0]
+.macro wait, count
+ mov r0, \count
+0:
+ subs r0, r0, #1
+ bne 0b
+.endm
- ldr r0, =GAFR2_L
- ldr r1, =0xA0000000
- str r1, [r0]
+ledflash:
+ mov r2, lr
+ bl ledset
+ wait #0x400000
+ bl ledclear
+ wait #0x400000
+ mov pc, r2
- ldr r0, =GAFR2_U
- ldr r1, =0x00000002
- str r1, [r0]
+endless_blink:
+ mov r4, r3
+0:
+ bl ledflash
+ subs r4, r4, #1
+ bne 0b
+ wait #0x2000000
+ b endless_blink
- mov pc, lr
-#endif
Index: start-sa11x0.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-sa11x0.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- start-sa11x0.S 26 Jul 2002 07:22:36 -0000 1.5
+++ start-sa11x0.S 6 Aug 2003 22:55:41 -0000 1.6
@@ -120,6 +120,9 @@
real_reset:
+ /* init GPIOs */
+ bl gpiosetup
+
/* init LED */
bl ledinit
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- start.S 10 Feb 2003 23:07:06 -0000 1.11
+++ start.S 6 Aug 2003 22:55:41 -0000 1.12
@@ -47,7 +47,8 @@
/* Jump vector table as in table 3.1 in [1] */
.globl _start
-_start: b reset
+_start:
+ b reset
b undefined_instruction
b software_interrupt
b prefetch_abort
@@ -57,29 +58,27 @@
b fiq
/* some defines to make life easier */
-/* main memory starts at 0xc0000000 */
BLOB_START: .word BLOB_ABS_BASE_ADDR
piggy_start: .word __piggy_start
piggy_end: .word __piggy_end
-
+.align
.globl normal_boot
normal_boot:
/* check the first 1MB of BLOB_START in increments of 4k */
- mov r7, #0x1000
- mov r6, r7, lsl #8 /* 4k << 2^8 = 1MB */
- ldr r5, BLOB_START
+ mov r7, #0x1000
+ mov r6, r7, lsl #8 /* 4KB << 8 = 1MB */
+ ldr r5, BLOB_START
mem_test_loop:
- mov r0, r5
- bl testram
- teq r0, #1
- beq endless_loop /* oops, something went wrong :( */
+ mov r0, r5
+ bl testram
+ teq r0, #1
+ beq endless_loop /* oops, something went wrong :( */
- add r5, r5, r7
+ add r5, r5, r7
subs r6, r6, r7
- bne mem_test_loop
-
+ bne mem_test_loop
relocate:
/* relocate the second stage loader */
@@ -102,7 +101,6 @@
cmp r0, r2
ble copy_loop
-
/* blob is copied to ram, so jump to it */
ldr r0, BLOB_START
mov pc, r0
@@ -114,3 +112,4 @@
* loop. FIXME! -- erik
*/
b endless_loop
+
Index: system3.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/system3.c,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- system3.c 3 Apr 2003 14:47:42 -0000 1.28
+++ system3.c 6 Aug 2003 22:55:41 -0000 1.29
@@ -46,7 +46,7 @@
#include <blob/partition.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
+#include <blob/arch.h>
#include <blob/sa1111.h>
#include <blob/generic_io.h>
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:55:44
|
Update of /cvsroot/blob/blob/src/commands
In directory sc8-pr-cvs1:/tmp/cvs-serv7704/src/commands
Modified Files:
Makefile.am setip.c sysupd.c tftp.c
Log Message:
Support for CSIR IMS board and also a working PXA25x port. Still needs some
cleaning up and the lubbock and PXA IDP targets are going to be broken by
this (not sure if they ever worked and fixing them is trivial).
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/commands/Makefile.am,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- Makefile.am 3 Apr 2003 14:39:11 -0000 1.6
+++ Makefile.am 6 Aug 2003 22:55:41 -0000 1.7
@@ -24,8 +24,11 @@
noinst_LIBRARIES = \
libcommands.a
-
libcommands_a_SOURCES = \
+ terminal.c \
+ reboot.c
+
+EXTRA_libcommands_a_SOURCES = \
call.c \
changebit.c \
dummy.c \
@@ -34,13 +37,11 @@
ferase.c \
fwrite.c \
memcpy.c \
- md5chk.c \
peek.c \
poke.c \
- reboot.c \
+ md5chk.c \
setip.c \
sysupd.c \
- terminal.c \
tftp.c
Index: setip.c
===================================================================
RCS file: /cvsroot/blob/blob/src/commands/setip.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- setip.c 3 Apr 2003 14:37:25 -0000 1.1
+++ setip.c 6 Aug 2003 22:55:41 -0000 1.2
@@ -31,6 +31,8 @@
# include <blob/config.h>
#endif
+#if defined( CONFIG_NETWORK_SUPPORT )
+
#include <blob/errno.h>
#include <blob/debug.h>
#include <blob/types.h>
@@ -38,10 +40,6 @@
#include <net/net.h>
-#if !defined( CONFIG_NETWORK_SUPPORT )
-# error "You must enable NETWORK support."
-#endif
-
/**********************************************************************
* defines
*/
@@ -111,3 +109,6 @@
char setip_help[] = "setip command. Set IP addresses for tftp.\n"
"usage: setip {client|server} ip\n"
"\tip in usual dotted-quad format please.\n";;
+
+#endif
+
Index: sysupd.c
===================================================================
RCS file: /cvsroot/blob/blob/src/commands/sysupd.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sysupd.c 3 Apr 2003 14:37:25 -0000 1.1
+++ sysupd.c 6 Aug 2003 22:55:41 -0000 1.2
@@ -32,6 +32,8 @@
# include <blob/config.h>
#endif
+#if defined( CONFIG_GIO_SUPPORT )
+
#include <blob/errno.h>
#include <blob/debug.h>
#include <blob/types.h>
@@ -44,10 +46,6 @@
#include <blob/ide.h>
#include <blob/tar.h>
-#if !defined( CONFIG_GIO_SUPPORT )
-# error "You must also enable PCMCIA and gereric IO support."
-#endif
-
/* these are the default images */
static char *update_files[] = {
"blob",
@@ -177,3 +175,6 @@
char sysupd_help[] = "sysupd [CF|RAM] [image [image]...]\n\nUpdate board firmware from CF card or RAM.\n"
"You have to have a update CF card inserted (for CF updates) _or_ uploaded a\n"
"update image to ram.";
+
+#endif
+
Index: tftp.c
===================================================================
RCS file: /cvsroot/blob/blob/src/commands/tftp.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- tftp.c 3 Apr 2003 14:37:25 -0000 1.1
+++ tftp.c 6 Aug 2003 22:55:41 -0000 1.2
@@ -37,9 +37,7 @@
#include <net/net.h>
-#if !defined( CONFIG_NETWORK_SUPPORT )
-# error "You must enable NETWORK support."
-#endif
+#if defined( CONFIG_NETWORK_SUPPORT )
#if !defined( RAM_START )
# error "Please define RAM_START for your arch!"
@@ -93,3 +91,6 @@
"usage: tftp filename\n"
"\tdownloads file over TFTP to RAM.\n"
"\tUse setip to set client and server IP addresses\n";
+
+#endif
+
|
|
From: Abraham vd M. <ab...@us...> - 2003-08-06 22:55:44
|
Update of /cvsroot/blob/blob/include/blob/proc In directory sc8-pr-cvs1:/tmp/cvs-serv7704/include/blob/proc Modified Files: pxa.h Log Message: Support for CSIR IMS board and also a working PXA25x port. Still needs some cleaning up and the lubbock and PXA IDP targets are going to be broken by this (not sure if they ever worked and fixing them is trivial). Index: pxa.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/proc/pxa.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- pxa.h 14 Aug 2002 20:59:53 -0000 1.1 +++ pxa.h 6 Aug 2003 22:55:40 -0000 1.2 @@ -30,8 +30,13 @@ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff */ -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) +/* +#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) +#define io_v2p(x) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) + */ + +#define io_p2v(x) (x) +#define io_v2p(x) (x) #ifndef __ASSEMBLY__ @@ -56,38 +61,164 @@ #include <asm-arm/arch-pxa/pxa-regs.h> /* memory start and end */ -/* are these values proc or arch specific? */ #define MEMORY_START (0xa0000000) -#define MEMORY_END (0xc0000000) +#define MEMORY_END (0xb0000000) -/********************************************************************** - * Memory Config Register Indices - * based on 0xA0000000 - */ +#define GPIO_OUT_LO_BIT 4 +#define GPIO_OUT_HI_BIT 5 -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 +#define GPIO_INPUT 0 +#define GPIO_OUT_LO (1 << GPIO_OUT_LO_BIT) +#define GPIO_OUT_HI (1 << GPIO_OUT_HI_BIT) -#define MDCNFG_DE0 (1 << 0) -#define MDCNFG_DE1 (1 << 1) -#define MDCNFG_DE2 (1 << 16) -#define MDCNFG_DE3 (1 << 17) -#define MDCNFG_DWID0_32B (0 << 3) +#define GPIO_ALT_FN1 0x01 +#define GPIO_ALT_FN2 0x02 +#define GPIO_ALT_FN3 0x03 +#define GPIO_ALT_FN_MASK (GPIO_ALT_FN1 | GPIO_ALT_FN2 | GPIO_ALT_FN3) -#endif +#define _SB(x) (((x) & GPIO_OUT_HI) >> GPIO_OUT_HI_BIT) +#define _SM(x) (_SB(GPIO##x##_VALUE) * GPIO_bit (x)) + +#define GPSR0_VALUE ( \ + _SM(0) | _SM(1) | _SM(2) | _SM(3) | \ + _SM(4) | _SM(5) | _SM(6) | _SM(7) | \ + _SM(8) | _SM(9) | _SM(10) | _SM(11) | \ + _SM(12) | _SM(13) | _SM(14) | _SM(15) | \ + _SM(16) | _SM(17) | _SM(18) | _SM(19) | \ + _SM(20) | _SM(21) | _SM(22) | _SM(23) | \ + _SM(24) | _SM(25) | _SM(26) | _SM(27) | \ + _SM(28) | _SM(29) | _SM(30) | _SM(31) \ + ) + +#define GPSR1_VALUE ( \ + _SM(32) | _SM(33) | _SM(34) | _SM(35) | \ + _SM(36) | _SM(37) | _SM(38) | _SM(39) | \ + _SM(40) | _SM(41) | _SM(42) | _SM(43) | \ + _SM(44) | _SM(45) | _SM(46) | _SM(47) | \ + _SM(48) | _SM(49) | _SM(50) | _SM(51) | \ + _SM(52) | _SM(53) | _SM(54) | _SM(55) | \ + _SM(56) | _SM(57) | _SM(58) | _SM(59) | \ + _SM(60) | _SM(61) | _SM(62) | _SM(63) \ + ) + +#define GPSR2_VALUE ( \ + _SM(64) | _SM(65) | _SM(66) | _SM(67) | \ + _SM(68) | _SM(69) | _SM(70) | _SM(71) | \ + _SM(72) | _SM(73) | _SM(74) | _SM(75) | \ + _SM(76) | _SM(77) | _SM(78) | _SM(79) | \ + _SM(80) | _SM(81) | _SM(82) | _SM(83) | \ + _SM(84) \ + ) + +#define _CB(x) (((x) & GPIO_OUT_LO) >> GPIO_OUT_LO_BIT) +#define _CM(x) (_CB(GPIO##x##_VALUE) * GPIO_bit (x)) + +#define GPCR0_VALUE ( \ + _CM(0) | _CM(1) | _CM(2) | _CM(3) | \ + _CM(4) | _CM(5) | _CM(6) | _CM(7) | \ + _CM(8) | _CM(9) | _CM(10) | _CM(11) | \ + _CM(12) | _CM(13) | _CM(14) | _CM(15) | \ + _CM(16) | _CM(17) | _CM(18) | _CM(19) | \ + _CM(20) | _CM(21) | _CM(22) | _CM(23) | \ + _CM(24) | _CM(25) | _CM(26) | _CM(27) | \ + _CM(28) | _CM(29) | _CM(30) | _CM(31) \ + ) +#define GPCR1_VALUE ( \ + _CM(32) | _CM(33) | _CM(34) | _CM(35) | \ + _CM(36) | _CM(37) | _CM(38) | _CM(39) | \ + _CM(40) | _CM(41) | _CM(42) | _CM(43) | \ + _CM(44) | _CM(45) | _CM(46) | _CM(47) | \ + _CM(48) | _CM(49) | _CM(50) | _CM(51) | \ + _CM(52) | _CM(53) | _CM(54) | _CM(55) | \ + _CM(56) | _CM(57) | _CM(58) | _CM(59) | \ + _CM(60) | _CM(61) | _CM(62) | _CM(63) \ + ) + +#define GPCR2_VALUE ( \ + _CM(64) | _CM(65) | _CM(66) | _CM(67) | \ + _CM(68) | _CM(69) | _CM(70) | _CM(71) | \ + _CM(72) | _CM(73) | _CM(74) | _CM(75) | \ + _CM(76) | _CM(77) | _CM(78) | _CM(79) | \ + _CM(80) | _CM(81) | _CM(82) | _CM(83) | \ + _CM(84) \ + ) + +#define _DB(x) (_SB(x) | _CB(x)) +#define _DM(x) (_DB(GPIO##x##_VALUE) * GPIO_bit (x)) + +#define GPDR0_VALUE ( \ + _DM(0) | _DM(1) | _DM(2) | _DM(3) | \ + _DM(4) | _DM(5) | _DM(6) | _DM(7) | \ + _DM(8) | _DM(9) | _DM(10) | _DM(11) | \ + _DM(12) | _DM(13) | _DM(14) | _DM(15) | \ + _DM(16) | _DM(17) | _DM(18) | _DM(19) | \ + _DM(20) | _DM(21) | _DM(22) | _DM(23) | \ + _DM(24) | _DM(25) | _DM(26) | _DM(27) | \ + _DM(28) | _DM(29) | _DM(30) | _DM(31) \ + ) + +#define GPDR1_VALUE ( \ + _DM(32) | _DM(33) | _DM(34) | _DM(35) | \ + _DM(36) | _DM(37) | _DM(38) | _DM(39) | \ + _DM(40) | _DM(41) | _DM(42) | _DM(43) | \ + _DM(44) | _DM(45) | _DM(46) | _DM(47) | \ + _DM(48) | _DM(49) | _DM(50) | _DM(51) | \ + _DM(52) | _DM(53) | _DM(54) | _DM(55) | \ + _DM(56) | _DM(57) | _DM(58) | _DM(59) | \ + _DM(60) | _DM(61) | _DM(62) | _DM(63) \ + ) + +#define GPDR2_VALUE ( \ + _DM(64) | _DM(65) | _DM(66) | _DM(67) | \ + _DM(68) | _DM(69) | _DM(70) | _DM(71) | \ + _DM(72) | _DM(73) | _DM(74) | _DM(75) | \ + _DM(76) | _DM(77) | _DM(78) | _DM(79) | \ + _DM(80) | _DM(81) | _DM(82) | _DM(83) | \ + _DM(84) \ + ) + +#define _FB(x) ((x) & GPIO_ALT_FN_MASK) +#define _FM(x) (_FB(GPIO##x##_VALUE) << ((x) & 0x0f)) + +#define GAFR0_L_VALUE ( \ + _FM(0) | _FM(1) | _FM(2) | _FM(3) | \ + _FM(4) | _FM(5) | _FM(6) | _FM(7) | \ + _FM(8) | _FM(9) | _FM(10) | _FM(11) | \ + _FM(12) | _FM(13) | _FM(14) | _FM(15) \ + ) + +#define GAFR0_U_VALUE ( \ + _FM(16) | _FM(17) | _FM(18) | _FM(19) | \ + _FM(20) | _FM(21) | _FM(22) | _FM(23) | \ + _FM(24) | _FM(25) | _FM(26) | _FM(27) | \ + _FM(28) | _FM(29) | _FM(30) | _FM(31) \ + ) + +#define GAFR1_L_VALUE ( \ + _FM(32) | _FM(33) | _FM(34) | _FM(35) | \ + _FM(36) | _FM(37) | _FM(38) | _FM(39) | \ + _FM(40) | _FM(41) | _FM(42) | _FM(43) | \ + _FM(44) | _FM(45) | _FM(46) | _FM(47) \ + ) + +#define GAFR1_U_VALUE ( \ + _FM(48) | _FM(49) | _FM(50) | _FM(51) | \ + _FM(52) | _FM(53) | _FM(54) | _FM(55) | \ + _FM(56) | _FM(57) | _FM(58) | _FM(59) | \ + _FM(60) | _FM(61) | _FM(62) | _FM(63) \ + ) + +#define GAFR2_L_VALUE ( \ + _FM(64) | _FM(65) | _FM(66) | _FM(67) | \ + _FM(68) | _FM(69) | _FM(70) | _FM(71) | \ + _FM(72) | _FM(73) | _FM(74) | _FM(75) | \ + _FM(76) | _FM(77) | _FM(78) | _FM(79) \ + ) + +#define GAFR2_U_VALUE ( \ + _FM(80) | _FM(81) | _FM(82) | _FM(83) | \ + _FM(84) \ + ) + +#endif |
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