[B2-devel] Performance improvements

[Gwenole B. <gb...@di...>]

Hi,

I have committed a small improvement to the JIT, i.e. direct chaining of
basic blocks in the same page, which represent around 99.99% of cases for
"coin" benchmark from ssbench.

It's a clear win but I have not fully tested it yet. nbench benchmarks on
a P4 @ 1.8 GHz now yields a 7.3 slow down vs. native x86 execution. i.e.  
nbench.ppc under kpxrun vs. nbench.x86.

BTW, I noticed that sheepshaver_cpu::interrupt() is sometimes nested. This
should not happen since XLM_IRQ_NEST is normally checked in
HandleInterrupt() prior to invoking the real NanoKernel one. Atomic
operations are normally OK as they are derived from boehm's gc. I think I
could arrange the code for multiple interrupt handler stacks like in
native ppc mode, but I really think this should normally not happen...

This reminds me I apparently forgot to commit x86_64 spinlocks too.