[B2-devel] JIT improvements and future directions?

[Gwenole B. <gbe...@ma...>]

Hi,

I have just implemented sort of block inlining. It does still have to
generate BSR/RET instructions to have correct stack content but that's
easier anyway. However, this doesn't bring as much as expected, if
anything.  That's probably because BSR.L are not translated yet and I have
to check why.

Besides, I decided to have a look at the opcodes that should worth being
translated. After running the mixed-benchmark of Speedometer 4, I come to
the following top ten:

Rank  Opc      Count Name
000: 81fc    1858278 DIVS
001: e9c5     565147 BFEXTU
002: 61ff     470663 BSR
003: 007c     335196 ORSR
004: e9d3     281943 BFEXTU
005: 40c0     267858 MVSR2
006: efc6     248459 BFINS
007: e9c0     245098 BFEXTU
008: 40e7     195290 MVSR2
009: 46df     193867 MV2SR
010: e541     169805 ASL

Needless to say, I will have to self-motivate enough to mess out 
translation of bit-field instructions. DIVS is worth a try too. After 
those 11 most untranslated instructions that had to be run from the cache, 
come a lot of A-Traps. As shows the continued top20:

011: a829     147549 ILLEGAL
012: 46c0     139348 MV2SR
013: a030     134593 ILLEGAL
014: a0dd     131286 ILLEGAL
015: abf7     131264 ILLEGAL
016: e9d0     106180 BFEXTU
017: e9ee      92768 BFEXTU
018: a873      62307 ILLEGAL
019: f200      60323 FPP

For those, I don't remember whether the OS is supposed to save registers 
itself or not. In the former case, translated code could be further 
optimized by not unconditionally spilling 68k registers to their original 
locations.

WDYT?

On the other hand, I would like to stabilize the JIT compiler more. But I
need feedback and problems I can reproduce here. There is a true reason
why I want a B2 1.0 with m68k->x86 JIT out soon. ;-)

Bye,
Gwenole.