Re: [B2-devel] IEEE FPU build problems

[Brian J. <bjj...@us...>]

--- Gwenole Beauchesne <gb...@di...> wrote:
> Done something in CVS. That may still be wrong though. BTW, I read

Didn't seem to help... I got a freeze instead of simple wrong
results.

> at some page that the mips64 compiler can have sizeof(long double)
> == 16 but (i) does not have an IEEE-compliant format, (ii) is
> emulated in a pair of double registers? As such, I am wondering if
> disabling quad doubles isn't the safest solution at this point.

Yes, the CPU itself only does float and double.  The math(3m) man page
describes the issues with long double... basically, the compiler
fabricates them from two doubles.  So using 8-byte doubles is probably
the way to go on MIPS/IRIX.

I'll try configuring with ac_cv_type_long_double=no... that forces
SIZEOF_LONG_DOUBLE to 0...  and it seems to work!  Calculator produces
reasonable answers, and the Speedometer FPU benchmarks also produce
something besides garbage.  That's never worked before on SGI boxes!

There may be some precision or rounding issues... using 68030+fpu
mode, if I enter 1.1 in ClarisWorks spreadsheet, I get 1.099999999 in
the cell.  Using plain 68030 mode, I get 1.1.  (Although even then, I
get rounding errors after some calculations.  Eg. it says 1.1*2 =
2.199999999.)

Anyway, it sounds like we should disable long doubles for sgi
platforms, at least with MIPSPro compilers.

						Brian