Re: [avr-llvm-devel] Status update

[Weddington, E. <Eri...@at...>]

> -----Original Message-----
> From: Borja Ferrer [mailto:bor...@gm...]
> Sent: Tuesday, April 05, 2011 5:45 PM
> To: Weddington, Eric
> Cc: avr...@li...
> Subject: Re: [avr-llvm-devel] Status update
> 
> Hello Eric, I phrased that in a wrong way sorry :) Basically when i wrote
> that movws were going to be emitted always i meant that they were going to
> be emitted directly by the compiler and not manually inserted as it's
> currently happening. The current implementation searches for 8 bit moves
> and tries to transform 2 moves in a row to a single movw, but it's missing
> many cases so that's why they dont get always emitted. With the new
> implementation, since the compiler is emitting real 16bit moves we will
> have a movw when it's needed so there's no danger of getting movws lost.

Ah, ok. That makes more sense. Thanks for the clarification.

<snip>
 
> OFFTOPIC: During the past weeks i've been implementing a 4 stage pipelined
> MIPS core in Verilog for an FPGA for a master class project, and now i
> really have a good feeling of the beauty of what is inside the RISC cpus.
> It's nice to have different point of views: the programmer, the compiler,
> the CPU core hardware...

Very cool! :-)

Eric