Re: [avr-llvm-devel] New backend implementation

[Borja F. <bor...@gm...>]

Eric, we could start with 8 bit regs for now and if we find that we can make
register pairs work we can then switch to use them.

John, sadly expansion wont work here because LLVM is not able to split the
pairs into single regs thus it cant find any 16 bit instructions. If we work
with 8 bit regs it will expand the code correctly, in fact, i didnt even add
the setOperandAction line, LLVM will do it automatically. Custom lowering is
a possible solution but im unsure now if it's the best.
First i have to say that i tried custom lowering the add instruction without
success because it involved splitting regs (i managed to do this) but i
failed at rebuilding the pairs because it involved using a 16bit OR
instruction which needed custom lowering and this also needed a 16 bit OR so
the story loops forever. I tried this the second day of development so by
that time i didnt have a very clear view yet of the compiler, dont know if
by now i would be able to do it.
You may want to read the discussion i had in the LLVM dev list in here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-August/034203.html
search for the same subject in september aswell to read the whole thread.

I think we should stay away of customizing as much as possible and let LLVM
do the work, when i tried custom lowering i did it with DAG nodes and not by
inserting manually instructions with BuildMI() which is horrible in my
opinion because it takes away a lot of information to the codegen passes and
from what i've seen this is what GCC does, i took at look at GCC's .md file
and inside it you can find every single operation with custom assembly.
A test i did was a multiplication by a constant (something like short a = b
* 53, unsure now if this was the exact code), GCC would emit a mul and all
the add chain instructions being the high part of the constant 0 so all this
could have been saved, however LLVM noticed this and saved these mentioned
instructions, and i think this is caused because GCC's operations are all
manually written in the .md, i dont know too much about GCC so i may be
wrong though but the test im explaining is for real.
We could try customizing but only using DAG nodes, but notice this would
involve doing it for every single operation and size.

Currently the trouble i can think of using 8 bit regs is that we have to
tell LLVM to alloc 16 bit or wider data in odd:even pairs and how to bring
in the movws, but we can discuss this later on.