Re: [avr-llvm-devel] New backend implementation

[John M. <ato...@gm...>]

Hi Borja,

We haven't got to the point of testing values greater then 8 bits. I thought
these things were suppose to be taken care if in AVRISelLowering.cpp? I
haven't really looked into this much but doesn't the legalize action of *
Expand* take care of this? If not what about the custom lowering?

 setOperationAction(ISD::ADD,              MVT::i16,   Expand);



On Sun, Sep 26, 2010 at 10:00 AM, Borja Ferrer <bor...@gm...>wrote:

> I've been taking a look at the code and noticed an important design issue
> you took. It's about how registers are defined in the RegisterInfo.td file.
> Defining register pairs is a good idea and in fact i did the same because it
> simplifies many things, BUT, that brought some problems after i did more
> testing. I noticed it when i tried to do a 16bit addition. LLVM will store
> the operands in two different pairs but then it wont know how to perform the
> addition because all add/sub instructions (ignoring ADIW) work with 8 bit
> regs. What i supposed is that LLVM would be able to split the register pair
> into individual regs perform the addition and then fuse them again into the
> pair, but i was too optimisitc, it doesnt handle things that way. This issue
> was the subject of my first email to the LLVM dev list.
> So at the end i had to work only with 8 bit regs, that way LLVM is smart to
> expand arithmetic operators of any size into a chain of add/addc
> instructions in the case of the "+" operator. If you did the same assumption
> i did then probably you would have faced this once you tested this case, but
> if you did it for another purpose then we can discuss this further to see
> how solve this problem.
>
>
>
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