Re: [avr-llvm-devel] New backend implementation

[Weddington, E. <Eri...@at...>]

Hi Borja,

I think that, at this point, if you feel that a certain design decision needs to be changed because it will get us farther in generating code, then you should feel free to make those changes as you deem necessary.

If there are any issues, I'm sure that we'll discuss them here on the list.

Eric Weddington 

> -----Original Message-----
> From: Borja Ferrer [mailto:bor...@gm...] 
> Sent: Sunday, September 26, 2010 11:01 AM
> To: avr...@li...
> Subject: Re: [avr-llvm-devel] New backend implementation
> 
> I've been taking a look at the code and noticed an important 
> design issue you took. It's about how registers are defined 
> in the RegisterInfo.td file. Defining register pairs is a 
> good idea and in fact i did the same because it simplifies 
> many things, BUT, that brought some problems after i did more 
> testing. I noticed it when i tried to do a 16bit addition. 
> LLVM will store the operands in two different pairs but then 
> it wont know how to perform the addition because all add/sub 
> instructions (ignoring ADIW) work with 8 bit regs. What i 
> supposed is that LLVM would be able to split the register 
> pair into individual regs perform the addition and then fuse 
> them again into the pair, but i was too optimisitc, it doesnt 
> handle things that way. This issue was the subject of my 
> first email to the LLVM dev list.
> So at the end i had to work only with 8 bit regs, that way 
> LLVM is smart to expand arithmetic operators of any size into 
> a chain of add/addc instructions in the case of the "+" 
> operator. If you did the same assumption i did then probably 
> you would have faced this once you tested this case, but if 
> you did it for another purpose then we can discuss this 
> further to see how solve this problem.
> 
> 
>