#204 Incorrect SSSE3/SSE4.1/SSE4.2 detection

v2.5x
closed-fixed
Internals (76)
5
2010-01-21
2009-06-21
Anonymous
No

In cpuaccel.cpp the checks for SSSE3, SSE4.1 and SSE4.2 are off by one bit:

mov ebx,ecx
shr ebx,8 //SSSE3 is bit 8
and ebx,1
shl ebx,9
and ebx,00000200h //set bit 9
or ebp,ebx

mov ebx,ecx
shr ebx,18 //SSE4 is bit 18
and ebx,1
shl ebx,10
and ebx,00000400h //set bit 10
or ebp,ebx

mov ebx,ecx
shr ebx,19 //SSE4.2 is bit 19
and ebx,1
shl ebx,11
and ebx,00000800h //set bit 11
or ebp,ebx

The right shifts should be by 9, 19, and 20 respectively. See here: http://www.intel.com/Assets/PDF/appnote/241618.pdf page 24.

Discussion

  • Ian Brabham

    Ian Brabham - 2009-06-24
    • milestone: --> v2.5x
    • assigned_to: nobody --> ianb1957
    • status: open --> closed-accepted
     
  • Ian Brabham

    Ian Brabham - 2009-06-24

    Thanks anonymous person,

    Added to CVS

     
  • Ian Brabham

    Ian Brabham - 2010-01-21
    • status: closed-accepted --> closed-fixed
     

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