[Assorted-commits] SF.net SVN: assorted: [351] cpp-commons/trunk/src/commons

[<yan...@us...>]

Revision: 351
          http://assorted.svn.sourceforge.net/assorted/?rev=351&view=rev
Author:   yangzhang
Date:     2008-02-10 10:36:33 -0800 (Sun, 10 Feb 2008)

Log Message:
-----------
imported cpuid.h from numa-bench

Modified Paths:
--------------
    cpp-commons/trunk/src/commons/cppcommons.cpp

Added Paths:
-----------
    cpp-commons/trunk/src/commons/cpuid.h

Modified: cpp-commons/trunk/src/commons/cppcommons.cpp
===================================================================
--- cpp-commons/trunk/src/commons/cppcommons.cpp	2008-02-10 18:28:56 UTC (rev 350)
+++ cpp-commons/trunk/src/commons/cppcommons.cpp	2008-02-10 18:36:33 UTC (rev 351)
@@ -24,6 +24,7 @@
 #endif
 
 #include "commons/check.h"
+#include "commons/cpuid.h"
 #include "commons/files.h"
 #include "commons/strings.h"
 #include "commons/time.h"

Added: cpp-commons/trunk/src/commons/cpuid.h
===================================================================
--- cpp-commons/trunk/src/commons/cpuid.h	                        (rev 0)
+++ cpp-commons/trunk/src/commons/cpuid.h	2008-02-10 18:36:33 UTC (rev 351)
@@ -0,0 +1,71 @@
+//
+// This library would be a straightforward target for auto-generation from a
+// spec.
+//
+
+#ifndef _COMMONS_CPUID_H
+#define _COMMONS_CPUID_H
+
+namespace commons
+{
+
+  enum {
+    CACHE = 2,
+    CACHE_LINE_SIZES = 0x80000005
+  };
+
+#define cpuid(func,ax,bx,cx,dx)\
+          __asm__ __volatile__ ("cpuid":\
+          "=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) : "a" (func));
+
+  /**
+   * Given an extended general-purpose register (e.g. EAX), extract the high
+   * 8-bit register (AH).
+   */
+  inline unsigned char
+  high(unsigned int r)
+  {
+    return ((r >> 8) & 0xffU);
+  }
+
+  /**
+   * Given an extended general-purpose register (e.g. EAX), extract the low
+   * 8-bit register (AL).
+   */
+  inline unsigned char
+  low(unsigned int r)
+  {
+    return (r & 0xffU);
+  }
+
+  /**
+   * Get cache line size in bytes on an Intel CPU.
+   * References:
+   * http://softpixel.com/~cwright/programming/simd/cpuid.php
+   * http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedprojects/instructions/instruct32_hh/vc46.htm
+   */
+  inline unsigned short
+  cache_line_sizes_intel()
+  {
+    unsigned int a, b, c, d;
+    cpuid(1, a, b, c, d);
+    return (unsigned short) (high(b) * 8);
+  }
+
+  /**
+   * Get cache line sizes on an AMD CPU.
+   * Reference: http://softpixel.com/~cwright/programming/simd/cpuid.php
+   * Maybe look at: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf
+   */
+  inline void
+  cache_line_sizes_amd(unsigned char *iline, unsigned char *dline)
+  {
+    int a, b, c, d;
+    cpuid(CACHE_LINE_SIZES, a, b, c, d);
+    *dline = low(c);
+    *iline = low(d);
+  }
+
+}
+
+#endif


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