Functionality

• Initialization of the secure world, for example exception vectors, control registers and interrupts for the platform.
• Library support for CPU specific reset and power down sequences. This includes support for errata workarounds and the latest Arm DynamIQ CPUs.
• Drivers to enable standard initialization of Arm System IP, for example Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone Controller (TZC).
• A generic SCMI driver to interface with conforming power controllers, for example the Arm System Control Processor (SCP).
• SMC (Secure Monitor Call) handling, conforming to the SMC Calling Convention using an EL3 runtime services framework.
• PSCI library support for CPU, cluster and system power management use-cases. This library is pre-integrated with the AArch64 EL3 Runtime Software, and is also suitable for integration with other AArch32 EL3 Runtime Software, for example an AArch32 Secure OS.
• A minimal AArch32 Secure Payload (SP_MIN) to demonstrate PSCI library integration with AArch32 EL3 Runtime Software.
• Secure Monitor library code such as world switching, EL1 context management and interrupt routing. When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the AArch64 EL3 Runtime Software must be integrated with a dispatcher component (SPD) to customize the interaction with the SP.
• A Test SP/SPD to demonstrate AArch64 Secure Monitor functionality and SP interaction with PSCI.
• SPDs for the OP-TEE Secure OS, NVidia Trusted Little Kernel and Trusty Secure OS.
• A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication, Firmware Update (or recovery mode), and packaging of the various firmware images into a Firmware Image Package (FIP).
• Pre-integration of TBB with the Arm CryptoCell product, to take advantage of its hardware Root of Trust and crypto acceleration services.
• Reliability, Availability, and Serviceability (RAS) functionality, including
  • A Secure Partition Manager (SPM) to manage Secure Partitions in Secure-EL0, which can be used to implement simple management and security services.
  • An SDEI dispatcher to route interrupt-based SDEI events.
  • An Exception Handling Framework (EHF) that allows dispatching of EL3 interrupts to their registered handlers, to facilitate firmware-first error handling.
• A dynamic configuration framework that enables each of the firmware images to be configured at runtime if required by the platform. It also enables loading of a hardware configuration (for example, a kernel device tree) as part of the FIP, to be passed through the firmware stages.
• Support for alternative boot flows, for example to support platforms where the EL3 Runtime Software is loaded using other firmware or a separate secure system processor, or where a non-TF-A ROM expects BL2 to be loaded at EL3.
• Support for the GCC, LLVM and Arm Compiler 6 toolchains.
• Support combining several libraries into a self-called "romlib" image, that may be shared across images to reduce memory footprint. The romlib image is stored in ROM but is accessed through a jump-table that may be stored in read-write memory, allowing for the library code to be patched.

For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.

Platforms

Various AArch32 and AArch64 builds of this release has been tested on variants r0, r1 and r2 of the Juno Arm Development Platform.

Various AArch64 builds of this release have been tested on the following Arm Fixed Virtual Platforms (FVP) without shifted affinities that do not support threaded CPU cores (64-bit host machine only):

NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.

• FVP_Base_Aresx4
• FVP_Base_AEMv8A-AEMv8A
• FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502
• FVP_Base_AEMv8A-AEMv8A
• FVP_Base_RevC-2xAEMv8A
• FVP_Base_Cortex-A32x4
• FVP_Base_Cortex-A35x4
• FVP_Base_Cortex-A53x4
• FVP_Base_Cortex-A55x4+Cortex-A75x4
• FVP_Base_Cortex-A55x4
• FVP_Base_Cortex-A57x4-A53x4
• FVP_Base_Cortex-A57x4
• FVP_Base_Cortex-A72x4-A53x4
• FVP_Base_Cortex-A72x4
• FVP_Base_Cortex-A73x4-A53x4
• FVP_Base_Cortex-A73x4
• FVP_Base_Cortex-A75x4
• FVP_Base_Cortex-A76x4
• FVP_CSS_SGI-575 (Version 11.3 build 40)
• Foundation_Platform

The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities that do not support threaded CPU cores (64-bit host machine only).

• FVP_Base_AEMv8A-AEMv8A
• FVP_Base_Cortex-A32x4

The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from Arm. See the Arm FVP website.

All the above platforms have been tested with Linaro Release 18.04.

This release also contains the following platform support:

• Allwinner sun50i_64 and sun50i_h6
• ARM SGI-575 and SGM-775
• HiKey, HiKey960 and Poplar boards
• Marvell Armada 8K
• MediaTek MT6795 and MT8173 SoCs
• NVidia T132, T186 and T210 SoCs
• NXP QorIQ LS1043A, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
• QEMU emulator
• Raspberry Pi 3 board
• RockChip RK3328, RK3368 and RK3399 SoCs
• Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
• STMicroelectronics STM32MP1
• Texas Instruments K3 SoCs
• Xilinx Zynq UltraScale + MPSoC

Still to come

• More platform support.
• Position independent executable (PIE) support.
• Ongoing support for new architectural features, CPUs and System IP.
• Ongoing support for new Arm system architecture specifications.
• Ongoing security hardening, optimization and quality improvements.

For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.

IRC channel

Development discussion takes place on the #trusted-firmware-a channel on the Freenode IRC network. This is not an official support channel. If you have an issue to raise, please use the GitHub issue tracker.

Feedback and support

Arm welcomes any feedback on TF-A. If you think you have found a security vulnerability, please report this using the process defined in the TF-A Security Centre. For all other feedback, please use the GitHub issue tracker.

Arm licensees may contact Arm directly via their partner managers.

Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.