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The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. It is capable of booting Linux and running standard benchmarks, and its performance (measured in CoreMarks/MHz) is competitive with commercial cores. The project is intended primarily for hardware/architecture research and teaching, rather than production silicon, and typically is used in conjunction with SoC frameworks (for example via Chipyard) to integrate BOOM into larger systems.
Features
- Implements RISC-V RV64GC ISA (including general integer, compressed instructions, floating-point, and optional extensions)
- Out-of-order execution with register renaming, multiple issue, superscalar pipelines to improve instruction-level parallelism and performance
- Parameterizable core design (you can configure number of pipeline stages, caches, issue width etc.) so you can trade off performance vs area vs power etc
- Works in FPGA prototyping flows (e.g. Amazon EC2 F1 with FireSim) as well as ASIC design flows
- Support for Linux booting in some configurations (i.e. runs full privilege spec, OS support) in simulation / FPGA prototyping contexts
- Efficient microarchitecture design: unified physical register file, highly tuned front-end, aggressive branch prediction, etc.
Project Samples
